D>>>^C^Xroot@qbone:~# cat qunibone.log.csv 
id;timestamp;level;source;thread;file;line;message
0;20:38:10.009688;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1;20:38:10.010014;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff1c0b 8b0a107408060001 0800060400011c0b 8b0a1074c0a8019b 000000000000c0a8 019b000000000000 0000000000000000 00000000
2;20:38:10.010049;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
3;20:38:10.010624;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
4;20:38:10.010909;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
5;20:38:10.011145;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
6;20:38:10.011286;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
7;20:38:10.011303;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
8;20:38:10.011386;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
9;20:38:10.011401;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
10;20:38:10.011420;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
11;20:38:10.011661;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
12;20:38:10.011684;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
13;20:38:10.011776;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
14;20:38:10.011790;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
15;20:38:10.011813;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
16;20:38:10.011829;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
17;20:38:10.012600;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
18;20:38:10.069911;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
19;20:38:10.070178;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
20;20:38:10.070211;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
21;20:38:10.070504;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
22;20:38:10.070951;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01503100 blen=2048 desc=1372742
23;20:38:10.071230;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372752
24;20:38:10.071461;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
25;20:38:10.071563;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
26;20:38:10.071578;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
27;20:38:10.071656;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
28;20:38:10.071671;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
29;20:38:10.071688;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
30;20:38:10.071897;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
31;20:38:10.071918;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
32;20:38:10.072000;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
33;20:38:10.072012;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
34;20:38:10.072035;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
35;20:38:10.072051;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
36;20:38:10.072160;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
37;20:38:10.489675;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
38;20:38:10.490000;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffffc82b 96b611ec00060001 af81010000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 00000000
39;20:38:10.490038;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
40;20:38:10.490652;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
41;20:38:10.490932;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
42;20:38:10.491170;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
43;20:38:10.491309;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
44;20:38:10.491326;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
45;20:38:10.491406;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
46;20:38:10.491420;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
47;20:38:10.491438;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
48;20:38:10.491686;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
49;20:38:10.491709;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
50;20:38:10.491797;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
51;20:38:10.491810;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
52;20:38:10.491834;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
53;20:38:10.491850;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
54;20:38:10.492587;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
55;20:38:10.509856;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
56;20:38:10.510159;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
57;20:38:10.510191;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
58;20:38:10.510716;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01513100 blen=2048 desc=1372772
59;20:38:10.511021;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373002
60;20:38:10.511255;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
61;20:38:10.511394;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
62;20:38:10.511409;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
63;20:38:10.511490;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
64;20:38:10.511504;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
65;20:38:10.511523;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
66;20:38:10.511760;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
67;20:38:10.511783;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
68;20:38:10.511868;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
69;20:38:10.511881;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
70;20:38:10.511903;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
71;20:38:10.511919;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
72;20:38:10.512666;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
73;20:38:10.589823;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
74;20:38:10.590083;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
75;20:38:10.590119;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
76;20:38:10.590669;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01517100 blen=2048 desc=1373006
77;20:38:10.590973;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373016
78;20:38:10.591207;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
79;20:38:10.591307;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
80;20:38:10.591322;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
81;20:38:10.591447;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
82;20:38:10.591462;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
83;20:38:10.591481;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
84;20:38:10.591720;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
85;20:38:10.591742;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
86;20:38:10.591828;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
87;20:38:10.591841;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
88;20:38:10.591864;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
89;20:38:10.591879;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
90;20:38:10.591962;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
91;20:38:10.673328;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
92;20:38:10.673597;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
93;20:38:10.673675;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173242 access=0
94;20:38:10.673710;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
95;20:38:10.673732;Dbg;deqna;4726;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173242 csr=010521)
96;20:38:10.673877;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
97;20:38:10.673894;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
98;20:38:10.673921;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373242 (csr=010501)
99;20:38:10.673944;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373242 words=6
100;20:38:10.674663;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=98 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
101;20:38:10.675053;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001564 desc=1373252
102;20:38:10.675398;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=98 desc=1373242)
103;20:38:10.675504;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
104;20:38:10.675518;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
105;20:38:10.675597;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
106;20:38:10.675614;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373256 words=6
107;20:38:10.676007;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373256
108;20:38:10.676099;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
109;20:38:10.676113;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
110;20:38:10.676136;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
111;20:38:10.676153;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
112;20:38:10.676419;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
113;20:38:10.676439;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
114;20:38:10.676526;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
115;20:38:10.676538;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
116;20:38:10.676562;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
117;20:38:10.676578;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
118;20:38:10.677291;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
119;20:38:10.689862;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
120;20:38:10.690142;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234562870 4e38d94008004500 0054000000007101 d6198efb22cec0a8 011e00006ca88000 05005769074e0600 be9c08090a0b0c0d 0e0f101112131415 
121;20:38:10.690215;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
122;20:38:10.690723;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01523100 blen=2048 desc=1373022
123;20:38:10.691097;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373032
124;20:38:10.691367;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
125;20:38:10.691468;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
126;20:38:10.691483;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
127;20:38:10.691562;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
128;20:38:10.691577;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
129;20:38:10.691595;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
130;20:38:10.691833;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
131;20:38:10.691856;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
132;20:38:10.691940;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
133;20:38:10.691952;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
134;20:38:10.691974;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
135;20:38:10.691990;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
136;20:38:10.692773;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
137;20:38:10.829226;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
138;20:38:10.829406;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0011000000000000 0000000000000000 00000000
139;20:38:10.829429;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
140;20:38:10.829739;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
141;20:38:10.829928;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
142;20:38:10.830054;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
143;20:38:10.830112;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
144;20:38:10.830120;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
145;20:38:10.830160;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
146;20:38:10.830167;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
147;20:38:10.830177;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
148;20:38:10.830381;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
149;20:38:10.830396;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
150;20:38:10.830444;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
151;20:38:10.830451;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
152;20:38:10.830463;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
153;20:38:10.830471;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
154;20:38:10.830537;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
155;20:38:10.831247;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
156;20:38:10.831370;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01a6000000000000 0000000000000000 00000000
157;20:38:10.831388;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
158;20:38:10.831655;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01533100 blen=2048 desc=1373052
159;20:38:10.831826;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373062
160;20:38:10.831948;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
161;20:38:10.831998;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
162;20:38:10.832005;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
163;20:38:10.832043;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
164;20:38:10.832050;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
165;20:38:10.832059;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
166;20:38:10.833112;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
167;20:38:10.833228;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 009a000000000000 0000000000000000 00000000
168;20:38:10.833245;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
169;20:38:10.833486;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01537100 blen=2048 desc=1373066
170;20:38:10.833617;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
171;20:38:10.833627;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
172;20:38:10.833685;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
173;20:38:10.833692;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
174;20:38:10.833704;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
175;20:38:10.833713;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
176;20:38:10.833776;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
177;20:38:10.833815;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373076
178;20:38:10.833914;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
179;20:38:10.833962;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
180;20:38:10.833969;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
181;20:38:10.834009;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
182;20:38:10.834016;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
183;20:38:10.834025;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
184;20:38:10.834200;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
185;20:38:10.834210;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
186;20:38:10.834252;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
187;20:38:10.834259;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
188;20:38:10.834270;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
189;20:38:10.834278;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
190;20:38:10.834821;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
191;20:38:10.869277;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=219 status=000000 queue=0
192;20:38:10.869431;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=219 data=ffffffffffff0010 752b42e908004500 00cd000040004011 781ec0a8015affff ffffe2a004d200b9 64ea48656c6c6f20 74686572652e2049 20616d2061742031 
193;20:38:10.869453;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
194;20:38:10.869740;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=219 to addr=01543100 blen=2048 desc=1373102
195;20:38:10.870281;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=117637 desc=1373112
196;20:38:10.870409;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
197;20:38:10.870464;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
198;20:38:10.870472;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
199;20:38:10.870513;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
200;20:38:10.870520;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
201;20:38:10.870529;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
202;20:38:10.870705;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
203;20:38:10.870718;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
204;20:38:10.870765;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
205;20:38:10.870772;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
206;20:38:10.870783;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
207;20:38:10.870791;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
208;20:38:10.871014;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
209;20:38:10.871593;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=243 status=000000 queue=0
210;20:38:10.871727;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=243 data=ffffffffffff0010 752b42e908004500 00e5000040004011 7806c0a8015affff ffffe2a1d01a00d1 b9b048656c6c6f20 74686572652e2049 20616d2061742031 
211;20:38:10.871744;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
212;20:38:10.871968;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=243 to addr=01547100 blen=2048 desc=1373116
213;20:38:10.872462;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=133667 desc=1373126
214;20:38:10.872581;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
215;20:38:10.872630;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
216;20:38:10.872637;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
217;20:38:10.872677;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
218;20:38:10.872684;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
219;20:38:10.872693;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
220;20:38:10.872858;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
221;20:38:10.872869;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
222;20:38:10.872911;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
223;20:38:10.872918;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
224;20:38:10.872929;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
225;20:38:10.872936;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
226;20:38:10.873093;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
227;20:38:10.873748;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
228;20:38:10.873864;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0016000000000000 0000000000000000 00000000
229;20:38:10.873882;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
230;20:38:10.874098;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01553100 blen=2048 desc=1373132
231;20:38:10.874277;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373142
232;20:38:10.874399;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
233;20:38:10.874447;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
234;20:38:10.874454;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
235;20:38:10.874494;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
236;20:38:10.874501;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
237;20:38:10.874510;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
238;20:38:10.874673;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
239;20:38:10.874683;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
240;20:38:10.874725;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
241;20:38:10.874731;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
242;20:38:10.874743;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
243;20:38:10.874751;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
244;20:38:10.875192;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
245;20:38:10.875564;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
246;20:38:10.875679;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0178000000000000 0000000000000000 00000000
247;20:38:10.875695;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
248;20:38:10.875907;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01557100 blen=2048 desc=1373146
249;20:38:10.876070;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373156
250;20:38:10.876189;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
251;20:38:10.876253;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
252;20:38:10.876261;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
253;20:38:10.876300;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
254;20:38:10.876307;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
255;20:38:10.876316;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
256;20:38:10.876487;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
257;20:38:10.876496;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
258;20:38:10.876538;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
259;20:38:10.876544;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
260;20:38:10.876555;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
261;20:38:10.876563;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
262;20:38:10.877385;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
263;20:38:10.877411;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
264;20:38:10.877523;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01ad000000000000 0000000000000000 00000000
265;20:38:10.877540;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
266;20:38:10.877799;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
267;20:38:10.877998;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
268;20:38:10.878131;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
269;20:38:10.878181;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
270;20:38:10.878188;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
271;20:38:10.878227;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
272;20:38:10.878234;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
273;20:38:10.878242;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
274;20:38:10.878416;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
275;20:38:10.878426;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
276;20:38:10.878469;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
277;20:38:10.878475;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
278;20:38:10.878487;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
279;20:38:10.878495;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
280;20:38:10.878675;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
281;20:38:10.889607;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
282;20:38:10.889742;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0131000000000000 0000000000000000 00000000
283;20:38:10.889762;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
284;20:38:10.889927;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
285;20:38:10.890192;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01503100 blen=2048 desc=1372742
286;20:38:10.890382;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372752
287;20:38:10.890524;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
288;20:38:10.890576;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
289;20:38:10.890584;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
290;20:38:10.890624;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
291;20:38:10.890630;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
292;20:38:10.890640;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
293;20:38:10.890819;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
294;20:38:10.890831;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
295;20:38:10.890875;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
296;20:38:10.890882;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
297;20:38:10.890893;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
298;20:38:10.890901;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
299;20:38:10.891142;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
300;20:38:10.891702;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
301;20:38:10.891821;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01b4000000000000 0000000000000000 00000000
302;20:38:10.891839;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
303;20:38:10.892069;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
304;20:38:10.892270;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
305;20:38:10.892392;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
306;20:38:10.892440;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
307;20:38:10.892447;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
308;20:38:10.892486;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
309;20:38:10.892493;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
310;20:38:10.892501;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
311;20:38:10.892666;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
312;20:38:10.892677;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
313;20:38:10.892719;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
314;20:38:10.892725;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
315;20:38:10.892736;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
316;20:38:10.892744;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
317;20:38:10.893226;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
318;20:38:10.909256;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
319;20:38:10.909399;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01b7000000000000 0000000000000000 00000000
320;20:38:10.909423;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
321;20:38:10.909724;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01513100 blen=2048 desc=1372772
322;20:38:10.909910;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373002
323;20:38:10.910035;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
324;20:38:10.910089;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
325;20:38:10.910096;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
326;20:38:10.910135;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
327;20:38:10.910142;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
328;20:38:10.910152;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
329;20:38:10.910328;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
330;20:38:10.910341;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
331;20:38:10.910384;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
332;20:38:10.910390;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
333;20:38:10.910402;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
334;20:38:10.910410;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
335;20:38:10.910820;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
336;20:38:11.069823;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
337;20:38:11.070098;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
338;20:38:11.070132;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
339;20:38:11.070706;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01517100 blen=2048 desc=1373006
340;20:38:11.070989;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373016
341;20:38:11.071222;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
342;20:38:11.071325;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
343;20:38:11.071340;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
344;20:38:11.071419;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
345;20:38:11.071434;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
346;20:38:11.071453;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
347;20:38:11.071664;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
348;20:38:11.071715;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
349;20:38:11.071804;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
350;20:38:11.071817;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
351;20:38:11.071840;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
352;20:38:11.071858;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
353;20:38:11.071941;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
354;20:38:11.269820;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
355;20:38:11.270098;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff0010 7f78e6ec08060001 0800060400010010 7f78e6ecc0a801c4 000000000000c0a8 0015000000000000 0000000000000000 00000000
356;20:38:11.270131;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
357;20:38:11.270665;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01523100 blen=2048 desc=1373022
358;20:38:11.270950;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373032
359;20:38:11.271185;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
360;20:38:11.271323;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
361;20:38:11.271339;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
362;20:38:11.271419;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
363;20:38:11.271434;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
364;20:38:11.271453;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
365;20:38:11.271691;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
366;20:38:11.271714;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
367;20:38:11.271799;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
368;20:38:11.271812;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
369;20:38:11.271834;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
370;20:38:11.271850;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
371;20:38:11.272598;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
372;20:38:11.629848;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
373;20:38:11.630126;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
374;20:38:11.630161;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
375;20:38:11.630666;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
376;20:38:11.631030;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
377;20:38:11.631271;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
378;20:38:11.631374;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
379;20:38:11.631389;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
380;20:38:11.631467;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
381;20:38:11.631483;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
382;20:38:11.631502;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
383;20:38:11.631714;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
384;20:38:11.631735;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
385;20:38:11.631820;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
386;20:38:11.631833;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
387;20:38:11.631857;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
388;20:38:11.631874;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
389;20:38:11.631985;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
390;20:38:11.673581;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
391;20:38:11.673794;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
392;20:38:11.673969;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173256 access=0
393;20:38:11.674006;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
394;20:38:11.674028;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173256 csr=010521)
395;20:38:11.674116;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
396;20:38:11.674132;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
397;20:38:11.674155;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373256 (csr=010501)
398;20:38:11.674178;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373256 words=6
399;20:38:11.674896;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=98 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
400;20:38:11.675147;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001564 desc=1373266
401;20:38:11.675554;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=98 desc=1373256)
402;20:38:11.675659;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
403;20:38:11.675673;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
404;20:38:11.675751;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
405;20:38:11.675768;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373272 words=6
406;20:38:11.676169;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373272
407;20:38:11.676262;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
408;20:38:11.676276;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
409;20:38:11.676331;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
410;20:38:11.676350;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
411;20:38:11.676603;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
412;20:38:11.676623;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
413;20:38:11.676707;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
414;20:38:11.676720;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
415;20:38:11.676743;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
416;20:38:11.676759;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
417;20:38:11.677492;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
418;20:38:11.689817;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
419;20:38:11.690092;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234562870 4e38d94008004500 0054000000007101 d6198efb22cec0a8 011e00006aa88000 06005769084e0600 be9c08090a0b0c0d 0e0f101112131415 
420;20:38:11.690130;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
421;20:38:11.690653;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01533100 blen=2048 desc=1373052
422;20:38:11.690973;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373062
423;20:38:11.691211;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
424;20:38:11.691312;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
425;20:38:11.691326;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
426;20:38:11.691404;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
427;20:38:11.691418;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
428;20:38:11.691435;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
429;20:38:11.691696;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
430;20:38:11.691716;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
431;20:38:11.691800;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
432;20:38:11.691812;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
433;20:38:11.691834;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
434;20:38:11.691850;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
435;20:38:11.692559;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
436;20:38:11.709841;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
437;20:38:11.710138;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff245a 4c1db8a508060001 080006040001245a 4c1db8a5c0a80009 ffffffffffffc0a8 0101000000000000 0000000000000000 00000000
438;20:38:11.710170;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
439;20:38:11.710664;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01537100 blen=2048 desc=1373066
440;20:38:11.710937;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373076
441;20:38:11.711171;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
442;20:38:11.711270;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
443;20:38:11.711318;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
444;20:38:11.711400;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
445;20:38:11.711415;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
446;20:38:11.711433;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
447;20:38:11.711802;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
448;20:38:11.711826;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
449;20:38:11.711910;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
450;20:38:11.711923;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
451;20:38:11.711946;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
452;20:38:11.711962;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
453;20:38:11.712558;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
454;20:38:12.009249;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
455;20:38:12.009403;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff0241 d4d1bd2b08060001 0800060400010241 d4d1bd2bc0a801c2 000000000000c0a8 01c2000000000000 0000000000000000 00000000
456;20:38:12.009422;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
457;20:38:12.009728;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01543100 blen=2048 desc=1373102
458;20:38:12.009928;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373112
459;20:38:12.010070;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
460;20:38:12.010126;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
461;20:38:12.010135;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
462;20:38:12.010175;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
463;20:38:12.010183;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
464;20:38:12.010193;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
465;20:38:12.010393;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
466;20:38:12.010407;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
467;20:38:12.010452;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
468;20:38:12.010459;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
469;20:38:12.010471;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
470;20:38:12.010480;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
471;20:38:12.011272;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
472;20:38:12.011305;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
473;20:38:12.011426;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff1c0b 8b0a107408060001 0800060400011c0b 8b0a1074c0a8019b 000000000000c0a8 019b000000000000 0000000000000000 00000000
474;20:38:12.011441;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
475;20:38:12.011717;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01547100 blen=2048 desc=1373116
476;20:38:12.011888;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373126
477;20:38:12.012010;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
478;20:38:12.012059;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
479;20:38:12.012066;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
480;20:38:12.012106;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
481;20:38:12.012114;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
482;20:38:12.012122;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
483;20:38:12.012292;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
484;20:38:12.012302;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
485;20:38:12.012345;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
486;20:38:12.012351;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
487;20:38:12.012362;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
488;20:38:12.012371;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
489;20:38:12.012530;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
490;20:38:12.109231;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
491;20:38:12.109373;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
492;20:38:12.109391;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
493;20:38:12.109668;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01553100 blen=2048 desc=1373132
494;20:38:12.109846;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373142
495;20:38:12.109974;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
496;20:38:12.110026;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
497;20:38:12.110034;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
498;20:38:12.110074;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
499;20:38:12.110081;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
500;20:38:12.110090;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
501;20:38:12.110276;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
502;20:38:12.110289;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
503;20:38:12.110331;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
504;20:38:12.110338;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
505;20:38:12.110349;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
506;20:38:12.110358;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
507;20:38:12.110396;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
508;20:38:12.469662;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
509;20:38:12.469941;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
510;20:38:12.469974;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
511;20:38:12.470514;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01557100 blen=2048 desc=1373146
512;20:38:12.470788;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373156
513;20:38:12.471033;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
514;20:38:12.471172;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
515;20:38:12.471187;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
516;20:38:12.471268;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
517;20:38:12.471283;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
518;20:38:12.471301;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
519;20:38:12.471542;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
520;20:38:12.471563;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
521;20:38:12.471647;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
522;20:38:12.471660;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
523;20:38:12.471683;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
524;20:38:12.471700;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
525;20:38:12.472449;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
526;20:38:12.669963;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
527;20:38:12.670231;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
528;20:38:12.670264;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
529;20:38:12.670752;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
530;20:38:12.671110;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
531;20:38:12.671350;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
532;20:38:12.671450;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
533;20:38:12.671466;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
534;20:38:12.671543;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
535;20:38:12.671557;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
536;20:38:12.671575;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
537;20:38:12.671785;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
538;20:38:12.671805;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
539;20:38:12.671890;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
540;20:38:12.671903;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
541;20:38:12.671926;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
542;20:38:12.671942;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
543;20:38:12.672052;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
544;20:38:12.674668;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
545;20:38:12.674902;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
546;20:38:12.674977;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173272 access=0
547;20:38:12.675009;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
548;20:38:12.675030;Dbg;deqna;4726;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173272 csr=010521)
549;20:38:12.675321;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
550;20:38:12.675339;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
551;20:38:12.675365;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373272 (csr=010501)
552;20:38:12.675388;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373272 words=6
553;20:38:12.676118;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=98 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
554;20:38:12.676423;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001564 desc=1373302
555;20:38:12.676776;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=98 desc=1373272)
556;20:38:12.676883;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
557;20:38:12.676897;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
558;20:38:12.676975;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
559;20:38:12.676991;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373306 words=6
560;20:38:12.677391;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373212 words=6
561;20:38:12.677787;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373212
562;20:38:12.677880;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
563;20:38:12.677893;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
564;20:38:12.677915;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
565;20:38:12.677933;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
566;20:38:12.678189;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
567;20:38:12.678209;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
568;20:38:12.678293;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
569;20:38:12.678306;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
570;20:38:12.678328;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
571;20:38:12.678343;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
572;20:38:12.679309;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
573;20:38:12.689840;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
574;20:38:12.690154;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234562870 4e38d94008004500 0054000000007101 d6198efb22cec0a8 011e000068a88000 07005769094e0600 be9c08090a0b0c0d 0e0f101112131415 
575;20:38:12.690193;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
576;20:38:12.690503;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
577;20:38:12.690921;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01503100 blen=2048 desc=1372742
578;20:38:12.691232;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1372752
579;20:38:12.691522;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
580;20:38:12.691623;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
581;20:38:12.691637;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
582;20:38:12.691713;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
583;20:38:12.691727;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
584;20:38:12.691745;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
585;20:38:12.691954;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
586;20:38:12.691975;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
587;20:38:12.692058;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
588;20:38:12.692071;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
589;20:38:12.692094;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
590;20:38:12.692111;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
591;20:38:12.692451;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
592;20:38:13.029255;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
593;20:38:13.029422;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff0010 7f78e6ec08060001 0800060400010010 7f78e6ecc0a801c4 000000000000c0a8 0015000000000000 0000000000000000 00000000
594;20:38:13.029446;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
595;20:38:13.029788;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
596;20:38:13.029977;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
597;20:38:13.030106;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
598;20:38:13.030164;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
599;20:38:13.030172;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
600;20:38:13.030213;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
601;20:38:13.030221;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
602;20:38:13.030250;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
603;20:38:13.030455;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
604;20:38:13.030471;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
605;20:38:13.030519;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
606;20:38:13.030525;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
607;20:38:13.030537;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
608;20:38:13.030546;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
609;20:38:13.031333;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
610;20:38:13.049224;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
611;20:38:13.049362;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008004500 0020ab3040004011 cdf3c0a80101ffff ffffc8782711000c 4da3010000000000 0000000000000000 00000000
612;20:38:13.049382;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
613;20:38:13.049652;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01513100 blen=2048 desc=1372772
614;20:38:13.049832;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373002
615;20:38:13.049957;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
616;20:38:13.050009;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
617;20:38:13.050017;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
618;20:38:13.050056;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
619;20:38:13.050063;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
620;20:38:13.050072;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
621;20:38:13.050268;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
622;20:38:13.050280;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
623;20:38:13.050323;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
624;20:38:13.050330;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
625;20:38:13.050341;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
626;20:38:13.050350;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
627;20:38:13.050388;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
628;20:38:13.089209;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=126 status=000000 queue=0
629;20:38:13.089353;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=126 data=ffffffffffff0800 2b038d9f08004500 0070c70c00004011 2f08c0a80119c0a8 01ff02010201005c 81040101000068ad 5f14000000006d69 6e65727661000000 
630;20:38:13.089394;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
631;20:38:13.089678;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=126 to addr=01517100 blen=2048 desc=1373006
632;20:38:13.089904;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=041102 desc=1373016
633;20:38:13.090033;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
634;20:38:13.090085;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
635;20:38:13.090093;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
636;20:38:13.090133;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
637;20:38:13.090141;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
638;20:38:13.090150;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
639;20:38:13.090322;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
640;20:38:13.090334;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
641;20:38:13.090377;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
642;20:38:13.090383;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
643;20:38:13.090394;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
644;20:38:13.090403;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
645;20:38:13.090488;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
646;20:38:13.149870;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
647;20:38:13.150166;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
648;20:38:13.150207;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
649;20:38:13.150742;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01523100 blen=2048 desc=1373022
650;20:38:13.151032;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373032
651;20:38:13.151272;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
652;20:38:13.151414;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
653;20:38:13.151432;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
654;20:38:13.151514;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
655;20:38:13.151528;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
656;20:38:13.151547;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
657;20:38:13.151788;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
658;20:38:13.151812;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
659;20:38:13.151902;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
660;20:38:13.151916;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
661;20:38:13.151939;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
662;20:38:13.151956;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
663;20:38:13.152693;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
664;20:38:13.369840;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
665;20:38:13.370116;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff7845 58f5956108060001 0800060400017845 58f59561c0a8000c ffffffffffffc0a8 0101000000000000 0000000000000000 00000000
666;20:38:13.370156;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
667;20:38:13.370720;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
668;20:38:13.371005;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
669;20:38:13.371241;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
670;20:38:13.371345;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
671;20:38:13.371361;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
672;20:38:13.371438;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
673;20:38:13.371452;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
674;20:38:13.371470;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
675;20:38:13.371713;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
676;20:38:13.371735;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
677;20:38:13.371821;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
678;20:38:13.371834;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
679;20:38:13.371896;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
680;20:38:13.371919;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
681;20:38:13.372003;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
682;20:38:13.529242;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
683;20:38:13.529396;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
684;20:38:13.529418;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
685;20:38:13.529712;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01533100 blen=2048 desc=1373052
686;20:38:13.529915;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373062
687;20:38:13.530044;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
688;20:38:13.530099;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
689;20:38:13.530107;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
690;20:38:13.530147;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
691;20:38:13.530154;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
692;20:38:13.530163;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
693;20:38:13.530345;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
694;20:38:13.530359;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
695;20:38:13.530406;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
696;20:38:13.530413;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
697;20:38:13.530425;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
698;20:38:13.530433;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
699;20:38:13.530827;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
700;20:38:13.675178;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
701;20:38:13.675325;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
702;20:38:13.675369;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173212 access=0
703;20:38:13.675387;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
704;20:38:13.675414;Dbg;deqna;4726;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173212 csr=010521)
705;20:38:13.675494;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
706;20:38:13.675504;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
707;20:38:13.675518;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373212 (csr=010501)
708;20:38:13.675530;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373212 words=6
709;20:38:13.675987;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=98 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
710;20:38:13.676616;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001564 desc=1373222
711;20:38:13.676825;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=98 desc=1373212)
712;20:38:13.676883;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
713;20:38:13.676892;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
714;20:38:13.676932;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
715;20:38:13.676940;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373226 words=6
716;20:38:13.677163;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373226
717;20:38:13.677211;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
718;20:38:13.677218;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
719;20:38:13.677230;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
720;20:38:13.677239;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
721;20:38:13.677435;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
722;20:38:13.677446;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
723;20:38:13.677489;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
724;20:38:13.677496;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
725;20:38:13.677508;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
726;20:38:13.677517;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
727;20:38:13.678325;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
728;20:38:13.689253;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
729;20:38:13.689398;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234562870 4e38d94008004500 0054000000007101 d6198efb22cec0a8 011e000066a88000 080057690a4e0600 be9c08090a0b0c0d 0e0f101112131415 
730;20:38:13.689420;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
731;20:38:13.689709;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01537100 blen=2048 desc=1373066
732;20:38:13.689920;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373076
733;20:38:13.690049;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
734;20:38:13.690102;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
735;20:38:13.690110;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
736;20:38:13.690150;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
737;20:38:13.690158;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
738;20:38:13.690167;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
739;20:38:13.690358;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
740;20:38:13.690369;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
741;20:38:13.690412;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
742;20:38:13.690419;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
743;20:38:13.690431;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
744;20:38:13.690440;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
745;20:38:13.690799;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
746;20:38:14.029716;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
747;20:38:14.029875;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff0010 7f78e6ec08060001 0800060400010010 7f78e6ecc0a801c4 000000000000c0a8 0015000000000000 0000000000000000 00000000
748;20:38:14.029897;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
749;20:38:14.030226;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01543100 blen=2048 desc=1373102
750;20:38:14.030397;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373112
751;20:38:14.030509;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
752;20:38:14.030563;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
753;20:38:14.030571;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
754;20:38:14.030605;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
755;20:38:14.030611;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
756;20:38:14.030619;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
757;20:38:14.030808;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
758;20:38:14.030823;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
759;20:38:14.030865;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
760;20:38:14.030871;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
761;20:38:14.030881;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
762;20:38:14.030889;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
763;20:38:14.031012;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
764;20:38:14.189142;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
765;20:38:14.189271;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
766;20:38:14.189290;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
767;20:38:14.189545;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01547100 blen=2048 desc=1373116
768;20:38:14.189716;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373126
769;20:38:14.189823;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
770;20:38:14.189888;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
771;20:38:14.189896;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
772;20:38:14.189931;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
773;20:38:14.189937;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
774;20:38:14.189946;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
775;20:38:14.190116;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
776;20:38:14.190128;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
777;20:38:14.190167;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
778;20:38:14.190173;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
779;20:38:14.190183;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
780;20:38:14.190190;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
781;20:38:14.191007;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
782;20:38:14.229130;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=121 status=000000 queue=0
783;20:38:14.229256;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=121 data=ffffffffffffb04a 39cb1cda08004500 006b000040004011 b67fc0a800b3c0a8 01ff97abe5f20057 f16c312e30000000 0100020040a00d54 b415c583cd296f58 
784;20:38:14.229275;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
785;20:38:14.229552;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=121 to addr=01553100 blen=2048 desc=1373132
786;20:38:14.229945;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=036475 desc=1373142
787;20:38:14.230052;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
788;20:38:14.230098;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
789;20:38:14.230104;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
790;20:38:14.230137;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
791;20:38:14.230144;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
792;20:38:14.230152;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
793;20:38:14.230314;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
794;20:38:14.230326;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
795;20:38:14.230364;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
796;20:38:14.230369;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
797;20:38:14.230397;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
798;20:38:14.230405;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
799;20:38:14.230441;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
800;20:38:14.549849;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
801;20:38:14.550164;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
802;20:38:14.550203;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
803;20:38:14.550736;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01557100 blen=2048 desc=1373146
804;20:38:14.551014;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373156
805;20:38:14.551249;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
806;20:38:14.551386;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
807;20:38:14.551401;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
808;20:38:14.551480;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
809;20:38:14.551494;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
810;20:38:14.551513;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
811;20:38:14.551752;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
812;20:38:14.551774;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
813;20:38:14.551859;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
814;20:38:14.551871;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
815;20:38:14.551894;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
816;20:38:14.551910;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
817;20:38:14.552654;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
818;20:38:14.589510;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
819;20:38:14.589767;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
820;20:38:14.589807;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
821;20:38:14.590322;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
822;20:38:14.590596;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
823;20:38:14.590829;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
824;20:38:14.590962;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
825;20:38:14.590977;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
826;20:38:14.591058;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
827;20:38:14.591072;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
828;20:38:14.591089;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
829;20:38:14.591326;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
830;20:38:14.591347;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
831;20:38:14.591431;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
832;20:38:14.591443;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
833;20:38:14.591466;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
834;20:38:14.591482;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
835;20:38:14.592234;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
836;20:38:14.672292;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
837;20:38:14.672412;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
838;20:38:14.672741;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173226 access=0
839;20:38:14.672764;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
840;20:38:14.672776;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173226 csr=010521)
841;20:38:14.672823;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
842;20:38:14.672831;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
843;20:38:14.672843;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373226 (csr=010501)
844;20:38:14.672855;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373226 words=6
845;20:38:14.673302;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=98 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
846;20:38:14.673454;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001564 desc=1373236
847;20:38:14.673656;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=98 desc=1373226)
848;20:38:14.673714;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
849;20:38:14.673722;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
850;20:38:14.673786;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
851;20:38:14.673795;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373242 words=6
852;20:38:14.674053;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373242
853;20:38:14.674102;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
854;20:38:14.674109;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
855;20:38:14.674120;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
856;20:38:14.674130;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
857;20:38:14.674331;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
858;20:38:14.674344;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
859;20:38:14.674390;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
860;20:38:14.674397;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
861;20:38:14.674409;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
862;20:38:14.674417;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
863;20:38:14.675182;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
864;20:38:14.689236;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
865;20:38:14.689380;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234562870 4e38d94008004500 0054000000007101 d6198efb22cec0a8 011e000064a88000 090057690b4e0600 be9c08090a0b0c0d 0e0f101112131415 
866;20:38:14.689405;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
867;20:38:14.689588;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
868;20:38:14.689839;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01503100 blen=2048 desc=1372742
869;20:38:14.690069;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1372752
870;20:38:14.690209;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
871;20:38:14.690263;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
872;20:38:14.690271;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
873;20:38:14.690312;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
874;20:38:14.690319;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
875;20:38:14.690329;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
876;20:38:14.690523;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
877;20:38:14.690535;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
878;20:38:14.690579;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
879;20:38:14.690585;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
880;20:38:14.690598;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
881;20:38:14.690607;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
882;20:38:14.690682;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
883;20:38:14.869669;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
884;20:38:14.869819;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=5254001234569803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 525400123456c0a8 011c000000000000 0000000000000000 00000000
885;20:38:14.869837;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
886;20:38:14.870151;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
887;20:38:14.870337;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
888;20:38:14.870463;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
889;20:38:14.870517;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
890;20:38:14.870525;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
891;20:38:14.870565;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
892;20:38:14.870572;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
893;20:38:14.870581;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
894;20:38:14.870776;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
895;20:38:14.870789;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
896;20:38:14.870833;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
897;20:38:14.870840;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
898;20:38:14.870852;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
899;20:38:14.870861;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
900;20:38:14.870948;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
901;20:38:14.871646;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
902;20:38:14.871770;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234569803 9bb4213e08004500 0054246500004001 d2c9c0a8010ec0a8 011c0800e482df20 000069581ea6000c c14e08090a0b0c0d 0e0f101112131415 
903;20:38:14.871790;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
904;20:38:14.872043;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01513100 blen=2048 desc=1372772
905;20:38:14.872244;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373002
906;20:38:14.872389;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
907;20:38:14.872439;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
908;20:38:14.872446;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
909;20:38:14.872486;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
910;20:38:14.872493;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
911;20:38:14.872502;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
912;20:38:14.873239;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
913;20:38:14.873250;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
914;20:38:14.873294;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
915;20:38:14.873301;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
916;20:38:14.873312;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
917;20:38:14.873321;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
918;20:38:14.873555;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
919;20:38:14.884285;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
920;20:38:14.884374;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173242 access=0
921;20:38:14.884463;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
922;20:38:14.885423;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
923;20:38:14.885443;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173242 csr=010521)
924;20:38:14.885490;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
925;20:38:14.885498;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
926;20:38:14.885510;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373242 (csr=010501)
927;20:38:14.885522;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373242 words=6
928;20:38:14.885915;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=60 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
929;20:38:14.886041;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001104 desc=1373252
930;20:38:14.886278;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=60 desc=1373242)
931;20:38:14.886334;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
932;20:38:14.886342;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
933;20:38:14.886382;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
934;20:38:14.886390;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373256 words=6
935;20:38:14.886754;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373256
936;20:38:14.886805;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
937;20:38:14.886812;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
938;20:38:14.886824;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
939;20:38:14.886832;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
940;20:38:14.887023;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
941;20:38:14.887034;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
942;20:38:14.887078;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
943;20:38:14.887084;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
944;20:38:14.887096;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
945;20:38:14.887104;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
946;20:38:14.887889;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
947;20:38:14.889134;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
948;20:38:14.889241;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
949;20:38:14.889497;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
950;20:38:14.889632;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=5254001234569803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 525400123456c0a8 011c000000000000 0000000000000000 00000000
951;20:38:14.889649;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
952;20:38:14.889884;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01517100 blen=2048 desc=1373006
953;20:38:14.889975;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173256 access=0
954;20:38:14.889993;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
955;20:38:14.890004;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173256 csr=010521)
956;20:38:14.890050;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
957;20:38:14.890057;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
958;20:38:14.890069;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373256 (csr=010501)
959;20:38:14.890168;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373016
960;20:38:14.890294;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
961;20:38:14.890346;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
962;20:38:14.890354;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010501 now=110501 set=100000 clr=000000
963;20:38:14.890395;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
964;20:38:14.890402;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110501 ie=1
965;20:38:14.890411;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110501 vec=374 level=5
966;20:38:14.890466;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373256 words=6
967;20:38:14.890570;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
968;20:38:14.890580;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
969;20:38:14.890622;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
970;20:38:14.890629;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110501 now=010501 set=000501 clr=103216
971;20:38:14.890640;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010501 ie=1
972;20:38:14.890648;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010501
973;20:38:14.890967;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=60 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
974;20:38:14.891077;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001104 desc=1373266
975;20:38:14.891260;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=60 desc=1373256)
976;20:38:14.891313;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
977;20:38:14.891320;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
978;20:38:14.891361;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
979;20:38:14.891369;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373272 words=6
980;20:38:14.891550;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010701 ie=1
981;20:38:14.891580;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
982;20:38:14.891704;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234569803 9bb4213e08004500 0054fa8900004001 fca4c0a8010ec0a8 011c0800b927df20 000169581ea6000c eca808090a0b0c0d 0e0f101112131415 
983;20:38:14.891913;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373272
984;20:38:14.891962;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
985;20:38:14.891969;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
986;20:38:14.891981;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
987;20:38:14.891989;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
988;20:38:14.892036;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
989;20:38:14.892256;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01523100 blen=2048 desc=1373022
990;20:38:14.892452;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373032
991;20:38:14.892573;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
992;20:38:14.892623;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110721/100701
993;20:38:14.892631;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010721 now=110721 set=100000 clr=000000
994;20:38:14.892670;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173256 XMTH=177526/000005 VECTOR=000774/000774 CSR=110721/100701
995;20:38:14.893084;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110721/100701
996;20:38:14.893132;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173272 access=0
997;20:38:14.893224;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110721/100701
998;20:38:14.893714;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
999;20:38:14.893731;Dbg;deqna;4726;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173272 csr=110721)
1000;20:38:14.893750;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1001;20:38:14.893863;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=5254001234569803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 525400123456c0a8 011c000000000000 0000000000000000 00000000
1002;20:38:14.893878;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
1003;20:38:14.894091;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
1004;20:38:14.894225;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110701/100701
1005;20:38:14.894233;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=110721 now=110701 set=000000 clr=000020
1006;20:38:14.894245;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373272 (csr=110701)
1007;20:38:14.894348;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
1008;20:38:14.894455;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110701/100701
1009;20:38:14.894465;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1010;20:38:14.894508;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1011;20:38:14.894515;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110701 now=010501 set=000501 clr=103216
1012;20:38:14.894526;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010501 ie=1
1013;20:38:14.894534;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010501
1014;20:38:14.894596;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
1015;20:38:14.894643;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
1016;20:38:14.894649;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010501 now=110501 set=100000 clr=000000
1017;20:38:14.894688;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
1018;20:38:14.894694;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110501 ie=1
1019;20:38:14.894703;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110501 vec=374 level=5
1020;20:38:14.894769;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373272 words=6
1021;20:38:14.895200;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=70 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=110501
1022;20:38:14.895308;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001224 desc=1373302
1023;20:38:14.895493;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=70 desc=1373272)
1024;20:38:14.895547;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110701/100701
1025;20:38:14.895555;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=110501 now=110701 set=000200 clr=000000
1026;20:38:14.895595;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110701/100701
1027;20:38:14.895603;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373306 words=6
1028;20:38:14.895844;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
1029;20:38:14.895973;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234569803 9bb4213e08004500 0054714f00004001 85dfc0a8010ec0a8 011c08008a3cdf20 000269581ea6000d 1b9208090a0b0c0d 0e0f101112131415 
1030;20:38:14.896013;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373212 words=6
1031;20:38:14.896245;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373212
1032;20:38:14.896293;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110721/100701
1033;20:38:14.896301;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=110701 now=110721 set=000220 clr=000000
1034;20:38:14.896339;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
1035;20:38:14.896551;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01533100 blen=2048 desc=1373052
1036;20:38:14.896760;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110721/100701
1037;20:38:14.896771;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1038;20:38:14.896816;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1039;20:38:14.896823;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110721 now=010521 set=000501 clr=103216
1040;20:38:14.896835;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1041;20:38:14.896843;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1042;20:38:14.896931;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373062
1043;20:38:14.897062;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
1044;20:38:14.897112;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1045;20:38:14.897119;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1046;20:38:14.897158;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1047;20:38:14.897165;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1048;20:38:14.897173;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1049;20:38:14.897366;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1050;20:38:14.897376;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1051;20:38:14.897419;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1052;20:38:14.897426;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1053;20:38:14.897437;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1054;20:38:14.897445;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1055;20:38:14.897483;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1056;20:38:14.909924;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1057;20:38:14.910190;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=5254001234569803 9bb4213e08060001 0800060400029803 9bb4213ec0a8010e 525400123456c0a8 011e000000000000 0000000000000000 00000000
1058;20:38:14.910222;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
1059;20:38:14.910725;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01537100 blen=2048 desc=1373066
1060;20:38:14.911069;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373076
1061;20:38:14.911324;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
1062;20:38:14.911427;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1063;20:38:14.911442;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1064;20:38:14.911521;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1065;20:38:14.911536;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1066;20:38:14.911555;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1067;20:38:14.912051;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1068;20:38:14.912076;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1069;20:38:14.912164;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1070;20:38:14.912178;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1071;20:38:14.912201;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1072;20:38:14.912218;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1073;20:38:14.912305;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1074;20:38:14.912720;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1075;20:38:14.912961;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=5254001234569803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 525400123456c0a8 011c000000000000 0000000000000000 00000000
1076;20:38:14.912994;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
1077;20:38:14.913499;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01543100 blen=2048 desc=1373102
1078;20:38:14.913777;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373112
1079;20:38:14.914011;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
1080;20:38:14.914109;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1081;20:38:14.914123;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1082;20:38:14.914200;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1083;20:38:14.914214;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1084;20:38:14.914231;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1085;20:38:14.914435;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1086;20:38:14.914455;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1087;20:38:14.914572;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1088;20:38:14.914585;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1089;20:38:14.914608;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1090;20:38:14.914625;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1091;20:38:14.914704;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1092;20:38:14.915378;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
1093;20:38:14.915623;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234569803 9bb4213e08004500 0054888900004001 6ea5c0a8010ec0a8 011c08005a7edf20 000369581ea6000d 4b4f08090a0b0c0d 0e0f101112131415 
1094;20:38:14.915660;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
1095;20:38:14.916137;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01547100 blen=2048 desc=1373116
1096;20:38:14.916444;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373126
1097;20:38:14.916689;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
1098;20:38:14.916783;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1099;20:38:14.916797;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1100;20:38:14.916907;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1101;20:38:14.916923;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1102;20:38:14.916942;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1103;20:38:14.917168;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1104;20:38:14.917187;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1105;20:38:14.917269;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1106;20:38:14.917282;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1107;20:38:14.917304;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1108;20:38:14.917320;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1109;20:38:14.918079;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1110;20:38:14.929874;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1111;20:38:14.930172;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=5254001234569803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 525400123456c0a8 011c000000000000 0000000000000000 00000000
1112;20:38:14.930204;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
1113;20:38:14.930701;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01553100 blen=2048 desc=1373132
1114;20:38:14.930997;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373142
1115;20:38:14.931230;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
1116;20:38:14.931363;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1117;20:38:14.931377;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1118;20:38:14.931457;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1119;20:38:14.931472;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1120;20:38:14.931491;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1121;20:38:14.931724;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1122;20:38:14.931746;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1123;20:38:14.931829;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1124;20:38:14.931842;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1125;20:38:14.931865;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1126;20:38:14.931881;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1127;20:38:14.932637;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1128;20:38:14.932686;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
1129;20:38:14.932923;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234569803 9bb4213e08004500 0054d8b000004001 1e7ec0a8010ec0a8 011c08002974df20 000469581ea6000d 7c5808090a0b0c0d 0e0f101112131415 
1130;20:38:14.932957;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
1131;20:38:14.933407;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01557100 blen=2048 desc=1373146
1132;20:38:14.933714;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373156
1133;20:38:14.933944;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
1134;20:38:14.934042;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1135;20:38:14.934055;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1136;20:38:14.934169;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1137;20:38:14.934183;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1138;20:38:14.934201;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1139;20:38:14.935348;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1140;20:38:14.935580;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=5254001234569803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 525400123456c0a8 011c000000000000 0000000000000000 00000000
1141;20:38:14.935613;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
1142;20:38:14.935838;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1143;20:38:14.935983;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1144;20:38:14.936298;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1145;20:38:14.936316;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1146;20:38:14.936424;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1147;20:38:14.936437;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1148;20:38:14.936461;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1149;20:38:14.936478;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1150;20:38:14.936566;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
1151;20:38:14.937095;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1152;20:38:14.937136;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173212 access=0
1153;20:38:14.937159;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1154;20:38:14.937178;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173212 csr=010521)
1155;20:38:14.937266;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1156;20:38:14.937280;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
1157;20:38:14.937304;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373212 (csr=010501)
1158;20:38:14.937372;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
1159;20:38:14.937619;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
1160;20:38:14.937715;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
1161;20:38:14.937729;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010501 now=110501 set=100000 clr=000000
1162;20:38:14.937806;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
1163;20:38:14.937819;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110501 ie=1
1164;20:38:14.937836;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110501 vec=374 level=5
1165;20:38:14.937932;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373212 words=6
1166;20:38:14.938140;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
1167;20:38:14.938159;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1168;20:38:14.938242;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1169;20:38:14.938254;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110501 now=010501 set=000501 clr=103216
1170;20:38:14.938277;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010501 ie=1
1171;20:38:14.938294;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010501
1172;20:38:14.939065;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010501 ie=1
1173;20:38:14.939119;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
1174;20:38:14.939361;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234569803 9bb4213e08004500 00541cb600004001 da78c0a8010ec0a8 011c0800f85adf20 000569581ea6000d ad7008090a0b0c0d 0e0f101112131415 
1175;20:38:14.939439;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=60 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
1176;20:38:14.939634;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001104 desc=1373222
1177;20:38:14.939962;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=60 desc=1373212)
1178;20:38:14.940065;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1179;20:38:14.940080;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
1180;20:38:14.940158;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1181;20:38:14.940174;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373226 words=6
1182;20:38:14.940571;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373226
1183;20:38:14.940664;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1184;20:38:14.940678;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
1185;20:38:14.940702;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1186;20:38:14.940718;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1187;20:38:14.940823;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
1188;20:38:14.941027;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1189;20:38:14.941046;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1190;20:38:14.941126;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1191;20:38:14.941138;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1192;20:38:14.941161;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1193;20:38:14.941177;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1194;20:38:14.941399;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
1195;20:38:14.941829;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01503100 blen=2048 desc=1372742
1196;20:38:14.941935;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1197;20:38:14.942146;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1372752
1198;20:38:14.942378;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
1199;20:38:14.942474;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1200;20:38:14.942489;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1201;20:38:14.942567;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1202;20:38:14.942581;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1203;20:38:14.942599;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1204;20:38:14.942802;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1205;20:38:14.942819;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1206;20:38:14.942900;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1207;20:38:14.942913;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1208;20:38:14.942934;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1209;20:38:14.942950;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1210;20:38:14.943052;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1211;20:38:14.944490;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1212;20:38:14.944702;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1213;20:38:14.945208;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173226 access=0
1214;20:38:14.945245;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1215;20:38:14.945265;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173226 csr=010521)
1216;20:38:14.945350;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1217;20:38:14.945362;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
1218;20:38:14.945385;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373226 (csr=010501)
1219;20:38:14.945405;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373226 words=6
1220;20:38:14.946110;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=70 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
1221;20:38:14.947139;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001224 desc=1373236
1222;20:38:14.947457;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=70 desc=1373226)
1223;20:38:14.947559;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1224;20:38:14.947572;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
1225;20:38:14.947650;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1226;20:38:14.947665;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373242 words=6
1227;20:38:14.948062;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373242
1228;20:38:14.948153;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1229;20:38:14.948167;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
1230;20:38:14.948189;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1231;20:38:14.948205;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1232;20:38:14.948781;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1233;20:38:14.948889;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1234;20:38:14.949202;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1235;20:38:14.949221;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1236;20:38:14.949359;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1237;20:38:14.949374;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1238;20:38:14.949397;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1239;20:38:14.949414;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1240;20:38:14.949516;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1241;20:38:14.949549;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173242 access=0
1242;20:38:14.949570;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1243;20:38:14.949589;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173242 csr=010521)
1244;20:38:14.949670;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1245;20:38:14.949683;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
1246;20:38:14.949706;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373242 (csr=010501)
1247;20:38:14.949725;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373242 words=6
1248;20:38:14.950410;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=60 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
1249;20:38:14.951597;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1250;20:38:14.951845;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff9803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 000000000000c0a8 011c000000000000 0000000000000000 00000000
1251;20:38:14.952031;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001104 desc=1373252
1252;20:38:14.952359;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=60 desc=1373242)
1253;20:38:14.952462;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1254;20:38:14.952476;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
1255;20:38:14.952553;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1256;20:38:14.952569;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373256 words=6
1257;20:38:14.952969;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373256
1258;20:38:14.953062;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1259;20:38:14.953076;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
1260;20:38:14.953098;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1261;20:38:14.953114;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1262;20:38:14.953223;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
1263;20:38:14.953425;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1264;20:38:14.953444;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1265;20:38:14.953528;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1266;20:38:14.953541;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1267;20:38:14.953563;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1268;20:38:14.953580;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1269;20:38:14.953880;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
1270;20:38:14.954202;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
1271;20:38:14.954346;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1272;20:38:14.954548;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
1273;20:38:14.954646;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1274;20:38:14.954660;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1275;20:38:14.954738;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1276;20:38:14.954753;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1277;20:38:14.954771;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1278;20:38:14.954977;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1279;20:38:14.954996;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1280;20:38:14.955078;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173242 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1281;20:38:14.955091;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1282;20:38:14.955114;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1283;20:38:14.955129;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1284;20:38:14.955446;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1285;20:38:14.959093;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1286;20:38:14.959358;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1287;20:38:14.959774;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173272 access=0
1288;20:38:14.959808;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1289;20:38:14.959829;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173272 csr=010521)
1290;20:38:14.959915;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1291;20:38:14.959927;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
1292;20:38:14.959950;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373272 (csr=010501)
1293;20:38:14.959970;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373272 words=6
1294;20:38:14.960709;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=60 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
1295;20:38:14.961542;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001104 desc=1373302
1296;20:38:14.961869;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=60 desc=1373272)
1297;20:38:14.961969;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1298;20:38:14.961983;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
1299;20:38:14.962062;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1300;20:38:14.962077;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373306 words=6
1301;20:38:14.962477;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373212 words=6
1302;20:38:14.962870;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373212
1303;20:38:14.962961;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1304;20:38:14.962975;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
1305;20:38:14.962998;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1306;20:38:14.963015;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1307;20:38:14.963404;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1308;20:38:14.963424;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1309;20:38:14.963507;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1310;20:38:14.963520;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1311;20:38:14.963543;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1312;20:38:14.963558;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1313;20:38:14.964138;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1314;20:38:14.967058;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1315;20:38:14.967298;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1316;20:38:14.967411;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173226 access=0
1317;20:38:14.967443;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1318;20:38:14.967463;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173226 csr=010521)
1319;20:38:14.967546;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1320;20:38:14.967557;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
1321;20:38:14.967579;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373226 (csr=010501)
1322;20:38:14.967600;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373226 words=6
1323;20:38:14.968274;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=60 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
1324;20:38:14.968429;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001104 desc=1373236
1325;20:38:14.968824;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=60 desc=1373226)
1326;20:38:14.968930;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1327;20:38:14.968943;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
1328;20:38:14.969021;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1329;20:38:14.969036;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373242 words=6
1330;20:38:14.969435;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373242
1331;20:38:14.969527;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1332;20:38:14.969542;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
1333;20:38:14.969564;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1334;20:38:14.969582;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1335;20:38:14.969837;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1336;20:38:14.969857;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1337;20:38:14.969940;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1338;20:38:14.969952;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1339;20:38:14.969976;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1340;20:38:14.969993;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1341;20:38:14.970743;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1342;20:38:15.029899;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1343;20:38:15.030168;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff0010 7f78e6ec08060001 0800060400010010 7f78e6ecc0a801c4 000000000000c0a8 0015000000000000 0000000000000000 00000000
1344;20:38:15.030205;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
1345;20:38:15.030687;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01513100 blen=2048 desc=1372772
1346;20:38:15.031058;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373002
1347;20:38:15.031299;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
1348;20:38:15.031402;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1349;20:38:15.031417;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1350;20:38:15.031494;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1351;20:38:15.031508;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1352;20:38:15.031525;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1353;20:38:15.031735;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1354;20:38:15.031757;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1355;20:38:15.031842;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1356;20:38:15.031854;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1357;20:38:15.031877;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1358;20:38:15.031893;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1359;20:38:15.032002;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1360;20:38:15.229166;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1361;20:38:15.229316;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
1362;20:38:15.229338;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
1363;20:38:15.229674;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01517100 blen=2048 desc=1373006
1364;20:38:15.229861;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373016
1365;20:38:15.229988;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
1366;20:38:15.230043;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1367;20:38:15.230052;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1368;20:38:15.230092;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1369;20:38:15.230100;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1370;20:38:15.230109;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1371;20:38:15.230297;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1372;20:38:15.230311;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1373;20:38:15.230357;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1374;20:38:15.230364;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1375;20:38:15.230376;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1376;20:38:15.230384;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1377;20:38:15.230480;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1378;20:38:15.589868;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1379;20:38:15.590152;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff74ac b933a1e908060001 08000604000174ac b933a1e9c0a80004 ffffffffffffc0a8 0101000000000000 0000000000000000 00000000
1380;20:38:15.590228;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
1381;20:38:15.590785;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01523100 blen=2048 desc=1373022
1382;20:38:15.591114;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373032
1383;20:38:15.591354;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
1384;20:38:15.591487;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1385;20:38:15.591503;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1386;20:38:15.591584;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1387;20:38:15.591597;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1388;20:38:15.591616;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1389;20:38:15.591859;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1390;20:38:15.591882;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1391;20:38:15.591970;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1392;20:38:15.591983;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1393;20:38:15.592006;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1394;20:38:15.592022;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1395;20:38:15.592766;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1396;20:38:15.609860;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1397;20:38:15.610158;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
1398;20:38:15.610197;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
1399;20:38:15.610714;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
1400;20:38:15.611013;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
1401;20:38:15.611246;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
1402;20:38:15.611382;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1403;20:38:15.611398;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1404;20:38:15.611477;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1405;20:38:15.611491;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1406;20:38:15.611510;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1407;20:38:15.611746;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1408;20:38:15.611767;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1409;20:38:15.611851;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1410;20:38:15.611864;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1411;20:38:15.611887;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1412;20:38:15.611903;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1413;20:38:15.612663;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1414;20:38:15.689903;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1415;20:38:15.690185;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff9803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 000000000000c0a8 011c000000000000 0000000000000000 00000000
1416;20:38:15.690227;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
1417;20:38:15.690758;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01533100 blen=2048 desc=1373052
1418;20:38:15.691075;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373062
1419;20:38:15.691315;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
1420;20:38:15.691421;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1421;20:38:15.691438;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1422;20:38:15.691516;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1423;20:38:15.691531;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1424;20:38:15.691549;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1425;20:38:15.691860;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1426;20:38:15.691883;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1427;20:38:15.692006;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1428;20:38:15.692020;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1429;20:38:15.692044;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1430;20:38:15.692061;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1431;20:38:15.692147;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1432;20:38:15.711143;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/000002
1433;20:38:15.711167;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 000002 access=0
1434;20:38:15.711255;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010022/000002
1435;20:38:15.711495;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010022/010020
1436;20:38:15.711514;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 010020 access=0
1437;20:38:15.711541;WRN;deqna;4720;deqna.cpp;1279;DEQNA: SW reset by driver (qerestart): prev_csr=010022 RI=0 XI=0 RL=0 XL=1 qlen=0 loss=0 rbdl=1373066 xbdl=1373242 tx_used=0/0 dma=0
1438;20:38:15.712046;Dbg;deqna;4720;deqna.cpp;946;DEQNA: sw_reset() begin csr=010022
1439;20:38:15.712139;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010060/010020
1440;20:38:15.712153;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010022 now=010060 set=000060 clr=177717
1441;20:38:15.712233;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010060/010020
1442;20:38:15.715077;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010060/100701
1443;20:38:15.715111;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1444;20:38:15.715203;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010561/100701
1445;20:38:15.715819;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO RCLL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010561/100701
1446;20:38:15.715927;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write RCLL (reg 2) = 172742 access=0
1447;20:38:15.716187;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO RCLH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010561/100701
1448;20:38:15.716643;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010561/100701
1449;20:38:15.716858;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010561/100701
1450;20:38:15.717141;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write RCLH (reg 3) = 000005 access=0
1451;20:38:15.717186;Dbg;deqna;4727;deqna.cpp;1207;DEQNA: RX list update pending (RCLH=000005 RCLL=172742 csr=010561)
1452;20:38:15.717208;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173212 access=0
1453;20:38:15.717227;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1454;20:38:15.717245;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173212 csr=010561)
1455;20:38:15.717334;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010541/100701
1456;20:38:15.717348;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010561 now=010541 set=000000 clr=000020
1457;20:38:15.717372;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373212 (csr=010541)
1458;20:38:15.717395;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373212 words=6
1459;20:38:15.718258;Dbg;deqna;4726;deqna.cpp;2640;DEQNA: RX list pending set (csr=010541)
1460;20:38:15.718368;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1461;20:38:15.718384;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010541 now=010501 set=000000 clr=000040
1462;20:38:15.718409;Dbg;deqna;4726;deqna.cpp;1430;DEQNA: RX list dispatch at 1372742 (csr=010501 queue=0)
1463;20:38:15.718509;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=128 setup=1 loopback=0 (IL_clear=0 EL_set=0) csr=010501
1464;20:38:15.720314;Dbg;deqna;4727;deqna.cpp;2370;DEQNA: Setup packet processed: len=128 promisc=0 multicast=0 flags=0000
1465;20:38:15.720371;Dbg;deqna;4727;deqna.cpp;2405;DEQNA: RING SNAPSHOT (setup processed) CSR=010501 rbdl=1372742 xbdl=1373212
1466;20:38:15.720725;Dbg;deqna;4727;deqna.cpp;2415;DEQNA: RBDL[0] @1372742 -> [100000 100006 103100 176000 100000 000000]
1467;20:38:15.720979;Dbg;deqna;4727;deqna.cpp;2415;DEQNA: RBDL[1] @1372756 -> [100000 100006 107100 176000 100000 000000]
1468;20:38:15.721210;Dbg;deqna;4727;deqna.cpp;2415;DEQNA: RBDL[2] @1372772 -> [100000 100006 113100 176000 100000 000000]
1469;20:38:15.721436;Dbg;deqna;4727;deqna.cpp;2415;DEQNA: RBDL[3] @1373006 -> [100000 100006 117100 176000 100000 000000]
1470;20:38:15.721662;Dbg;deqna;4727;deqna.cpp;2415;DEQNA: RBDL[4] @1373022 -> [100000 100006 123100 176000 100000 000000]
1471;20:38:15.721886;Dbg;deqna;4727;deqna.cpp;2415;DEQNA: RBDL[5] @1373036 -> [100000 100006 127100 176000 100000 000000]
1472;20:38:15.722112;Dbg;deqna;4727;deqna.cpp;2415;DEQNA: RBDL[6] @1373052 -> [100000 100006 133100 176000 100000 000000]
1473;20:38:15.722339;Dbg;deqna;4727;deqna.cpp;2415;DEQNA: RBDL[7] @1373066 -> [100000 100006 137100 176000 100000 000000]
1474;20:38:15.722616;Dbg;deqna;4727;deqna.cpp;2429;DEQNA: XBDL[0] @1373212 -> [177777 130005 173322 177700 100000 000000]
1475;20:38:15.722848;Dbg;deqna;4727;deqna.cpp;2429;DEQNA: XBDL[1] @1373226 -> [100000 120006 173100 177735 100000 001104]
1476;20:38:15.723074;Dbg;deqna;4727;deqna.cpp;2429;DEQNA: XBDL[2] @1373242 -> [100000 120006 177100 177742 100000 000000]
1477;20:38:15.723300;Dbg;deqna;4727;deqna.cpp;2429;DEQNA: XBDL[3] @1373256 -> [100000 120007 003100 177735 100000 000000]
1478;20:38:15.723525;Dbg;deqna;4727;deqna.cpp;2429;DEQNA: XBDL[4] @1373272 -> [100000 020007 007100 177742 100000 001104]
1479;20:38:15.723752;Dbg;deqna;4727;deqna.cpp;2429;DEQNA: XBDL[5] @1373306 -> [177777 140005 173212 000000 100000 000000]
1480;20:38:15.723977;Dbg;deqna;4727;deqna.cpp;2429;DEQNA: XBDL[6] @1373212 -> [177777 130005 173322 177700 100000 000000]
1481;20:38:15.724201;Dbg;deqna;4727;deqna.cpp;2429;DEQNA: XBDL[7] @1373226 -> [100000 120006 173100 177735 100000 001104]
1482;20:38:15.724243;Dbg;deqna;4727;deqna.cpp;1351;DEQNA: Enqueue RX type=0 len=128 status=000000 queue=0
1483;20:38:15.724287;Dbg;deqna;4727;deqna.cpp;2196;DEQNA: TX loopback/setup status st1=020014 st2=004140 desc=1373222
1484;20:38:15.724584;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1485;20:38:15.724603;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
1486;20:38:15.724629;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373226 words=6
1487;20:38:15.725291;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=70 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010701
1488;20:38:15.725513;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001224 desc=1373236
1489;20:38:15.725857;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=70 desc=1373226)
1490;20:38:15.725962;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1491;20:38:15.726032;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1492;20:38:15.726048;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373242 words=6
1493;20:38:15.726708;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=60 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010701
1494;20:38:15.726864;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001104 desc=1373252
1495;20:38:15.727156;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=60 desc=1373242)
1496;20:38:15.727254;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1497;20:38:15.727324;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1498;20:38:15.727338;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373256 words=6
1499;20:38:15.728054;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=70 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010701
1500;20:38:15.728196;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001224 desc=1373266
1501;20:38:15.728487;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=70 desc=1373256)
1502;20:38:15.728584;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1503;20:38:15.728783;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1504;20:38:15.728803;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373272 words=6
1505;20:38:15.729215;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373272
1506;20:38:15.729307;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1507;20:38:15.729322;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
1508;20:38:15.729344;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1509;20:38:15.729362;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1510;20:38:15.729514;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
1511;20:38:15.729911;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1512;20:38:15.729934;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1513;20:38:15.730022;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1514;20:38:15.730035;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1515;20:38:15.730058;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1516;20:38:15.730075;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1517;20:38:15.730183;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=0 rbl=128 to addr=01503100 blen=2048 desc=1372742
1518;20:38:15.730554;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1519;20:38:15.730650;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=0 st1=023400 st2=100200 desc=1372752
1520;20:38:15.730682;Dbg;deqna;4726;deqna.cpp;1790;DEQNA: RX status flags err=0 ovf=0 discard=0 lastnot=0 esetup=1 rbl=128
1521;20:38:15.730917;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
1522;20:38:15.731019;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1523;20:38:15.731034;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1524;20:38:15.731114;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1525;20:38:15.731130;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1526;20:38:15.731147;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1527;20:38:15.731793;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1528;20:38:15.731909;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1529;20:38:15.731988;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173272 access=0
1530;20:38:15.732022;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1531;20:38:15.732043;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173272 csr=110521)
1532;20:38:15.732129;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=100701/100701
1533;20:38:15.732142;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=110521 now=110501 set=000000 clr=000020
1534;20:38:15.732166;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373272 (csr=110501)
1535;20:38:15.732186;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373272 words=6
1536;20:38:15.732499;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
1537;20:38:15.732518;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1538;20:38:15.732602;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1539;20:38:15.732614;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110501 now=010501 set=000501 clr=103216
1540;20:38:15.732638;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010501 ie=1
1541;20:38:15.732656;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010501
1542;20:38:15.733411;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=98 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
1543;20:38:15.733670;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001564 desc=1373302
1544;20:38:15.733993;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=98 desc=1373272)
1545;20:38:15.734096;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1546;20:38:15.734110;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
1547;20:38:15.734188;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1548;20:38:15.734203;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373306 words=6
1549;20:38:15.734602;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373212 words=6
1550;20:38:15.734997;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373212
1551;20:38:15.735090;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1552;20:38:15.735104;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
1553;20:38:15.735126;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1554;20:38:15.735143;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1555;20:38:15.735407;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1556;20:38:15.735427;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1557;20:38:15.735512;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1558;20:38:15.735524;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1559;20:38:15.735548;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1560;20:38:15.735564;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1561;20:38:15.736315;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1562;20:38:15.749914;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
1563;20:38:15.750242;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234562870 4e38d94008004500 0054000000007101 d6198efb22cec0a8 011e000062a88000 0a0057690c4e0600 be9c08090a0b0c0d 0e0f101112131415 
1564;20:38:15.750282;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
1565;20:38:15.750829;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01507100 blen=2048 desc=1372756
1566;20:38:15.751158;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1372766
1567;20:38:15.751394;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
1568;20:38:15.751525;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1569;20:38:15.751539;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1570;20:38:15.751620;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1571;20:38:15.751634;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1572;20:38:15.751653;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1573;20:38:15.751893;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1574;20:38:15.751916;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1575;20:38:15.752001;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1576;20:38:15.752015;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1577;20:38:15.752037;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1578;20:38:15.752053;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1579;20:38:15.752814;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1580;20:38:15.869112;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=219 status=000000 queue=0
1581;20:38:15.869271;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=219 data=ffffffffffff0010 752b42e908004500 00cd000040004011 781ec0a8015affff ffffe2a004d200b9 5fea48656c6c6f20 74686572652e2049 20616d2061742031 
1582;20:38:15.869293;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
1583;20:38:15.869614;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=219 to addr=01513100 blen=2048 desc=1372772
1584;20:38:15.870123;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=117637 desc=1373002
1585;20:38:15.870254;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
1586;20:38:15.870310;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1587;20:38:15.870319;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1588;20:38:15.870359;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1589;20:38:15.870365;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1590;20:38:15.870394;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1591;20:38:15.870591;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1592;20:38:15.870604;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1593;20:38:15.870651;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1594;20:38:15.870658;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1595;20:38:15.870670;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1596;20:38:15.870678;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1597;20:38:15.871461;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1598;20:38:15.871488;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=243 status=000000 queue=0
1599;20:38:15.871611;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=243 data=ffffffffffff0010 752b42e908004500 00e5000040004011 7806c0a8015affff ffffe2a1d01a00d1 b4b048656c6c6f20 74686572652e2049 20616d2061742031 
1600;20:38:15.871628;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
1601;20:38:15.871873;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=243 to addr=01517100 blen=2048 desc=1373006
1602;20:38:15.872373;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=133667 desc=1373016
1603;20:38:15.872493;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
1604;20:38:15.872542;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1605;20:38:15.872549;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1606;20:38:15.872588;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1607;20:38:15.872595;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1608;20:38:15.872603;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1609;20:38:15.872722;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=110521 ie=1
1610;20:38:15.872743;Dbg;deqna;4727;deqna.cpp;725;DEQNA: INTR deassert, csr=110521
1611;20:38:15.872832;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1612;20:38:15.872842;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1613;20:38:15.872885;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1614;20:38:15.872892;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1615;20:38:16.269883;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1616;20:38:16.270230;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
1617;20:38:16.270277;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
1618;20:38:16.270864;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01523100 blen=2048 desc=1373022
1619;20:38:16.271157;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373032
1620;20:38:16.271394;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
1621;20:38:16.271536;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1622;20:38:16.271553;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1623;20:38:16.271634;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1624;20:38:16.271648;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1625;20:38:16.271668;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1626;20:38:16.271920;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1627;20:38:16.271943;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1628;20:38:16.272031;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1629;20:38:16.272044;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1630;20:38:16.272067;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1631;20:38:16.272084;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1632;20:38:16.272821;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1633;20:38:16.469386;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1634;20:38:16.469655;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
1635;20:38:16.469689;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
1636;20:38:16.470219;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
1637;20:38:16.470493;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
1638;20:38:16.470725;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
1639;20:38:16.470862;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1640;20:38:16.470878;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1641;20:38:16.470958;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1642;20:38:16.470972;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1643;20:38:16.470991;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1644;20:38:16.471232;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1645;20:38:16.471254;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1646;20:38:16.471340;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1647;20:38:16.471353;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1648;20:38:16.471376;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1649;20:38:16.471393;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1650;20:38:16.472134;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1651;20:38:16.629807;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1652;20:38:16.630120;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
1653;20:38:16.630153;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
1654;20:38:16.630675;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01533100 blen=2048 desc=1373052
1655;20:38:16.630959;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373062
1656;20:38:16.631194;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
1657;20:38:16.631332;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1658;20:38:16.631348;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1659;20:38:16.631428;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1660;20:38:16.631442;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1661;20:38:16.631460;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1662;20:38:16.631695;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1663;20:38:16.631717;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1664;20:38:16.631800;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1665;20:38:16.631813;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1666;20:38:16.631836;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1667;20:38:16.631853;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1668;20:38:16.632608;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1669;20:38:16.669307;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1670;20:38:16.669564;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff9803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 000000000000c0a8 011c000000000000 0000000000000000 00000000
1671;20:38:16.669596;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
1672;20:38:16.670092;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01537100 blen=2048 desc=1373066
1673;20:38:16.670359;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373076
1674;20:38:16.670587;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
1675;20:38:16.670686;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1676;20:38:16.670701;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1677;20:38:16.670813;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1678;20:38:16.670827;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1679;20:38:16.670846;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1680;20:38:16.671078;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1681;20:38:16.671098;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1682;20:38:16.671185;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173272 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1683;20:38:16.671198;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1684;20:38:16.671220;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1685;20:38:16.671236;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1686;20:38:16.671983;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1687;20:38:16.674584;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1688;20:38:16.674690;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1689;20:38:16.675288;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173212 access=0
1690;20:38:16.675329;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1691;20:38:16.675350;Dbg;deqna;4727;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173212 csr=010521)
1692;20:38:16.675439;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1693;20:38:16.675453;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
1694;20:38:16.675477;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373212 (csr=010501)
1695;20:38:16.675499;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373212 words=6
1696;20:38:16.676258;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=98 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=010501
1697;20:38:16.676506;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001564 desc=1373222
1698;20:38:16.676908;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=98 desc=1373212)
1699;20:38:16.677016;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1700;20:38:16.677031;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010701 set=000200 clr=000000
1701;20:38:16.677111;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010701/100701
1702;20:38:16.677129;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373226 words=6
1703;20:38:16.677531;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373226
1704;20:38:16.677624;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1705;20:38:16.677637;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010701 now=010721 set=000220 clr=000000
1706;20:38:16.677693;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1707;20:38:16.677710;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1708;20:38:16.677965;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1709;20:38:16.677984;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1710;20:38:16.678066;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1711;20:38:16.678079;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1712;20:38:16.678102;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1713;20:38:16.678119;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1714;20:38:16.678851;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1715;20:38:16.689513;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
1716;20:38:16.689829;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234562870 4e38d94008004500 0054000000007101 d6198efb22cec0a8 011e000060a88000 0b0057690d4e0600 be9c08090a0b0c0d 0e0f101112131415 
1717;20:38:16.689867;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
1718;20:38:16.690335;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01543100 blen=2048 desc=1373102
1719;20:38:16.690665;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373112
1720;20:38:16.690899;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
1721;20:38:16.690998;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1722;20:38:16.691014;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1723;20:38:16.691092;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1724;20:38:16.691106;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1725;20:38:16.691124;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1726;20:38:16.691333;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1727;20:38:16.691353;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1728;20:38:16.691435;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1729;20:38:16.691448;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1730;20:38:16.691471;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1731;20:38:16.691523;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1732;20:38:16.691605;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1733;20:38:17.029893;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1734;20:38:17.030186;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff0010 7f78e6ec08060001 0800060400010010 7f78e6ecc0a801c4 000000000000c0a8 0015000000000000 0000000000000000 00000000
1735;20:38:17.030222;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
1736;20:38:17.030750;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01547100 blen=2048 desc=1373116
1737;20:38:17.031066;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373126
1738;20:38:17.031305;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
1739;20:38:17.031410;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1740;20:38:17.031425;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1741;20:38:17.031503;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1742;20:38:17.031516;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1743;20:38:17.031534;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1744;20:38:17.031750;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1745;20:38:17.031772;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1746;20:38:17.031860;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1747;20:38:17.031873;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1748;20:38:17.031897;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1749;20:38:17.031944;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1750;20:38:17.032030;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1751;20:38:17.289892;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1752;20:38:17.290170;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffffd0d2 b08e8ca608060001 080006040001d0d2 b08e8ca6c0a8008b 000000000000c0a8 008b000000000000 0000000000000000 00000000
1753;20:38:17.290204;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
1754;20:38:17.290771;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01553100 blen=2048 desc=1373132
1755;20:38:17.291049;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373142
1756;20:38:17.291282;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
1757;20:38:17.291423;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1758;20:38:17.291439;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1759;20:38:17.291520;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1760;20:38:17.291534;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1761;20:38:17.291552;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1762;20:38:17.291793;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1763;20:38:17.291815;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1764;20:38:17.291901;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1765;20:38:17.291914;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1766;20:38:17.291937;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1767;20:38:17.291954;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1768;20:38:17.292695;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1769;20:38:17.309746;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1770;20:38:17.309892;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
1771;20:38:17.309909;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
1772;20:38:17.310218;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01557100 blen=2048 desc=1373146
1773;20:38:17.310396;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373156
1774;20:38:17.310522;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
1775;20:38:17.310576;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1776;20:38:17.310583;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1777;20:38:17.310623;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1778;20:38:17.310630;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1779;20:38:17.310639;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1780;20:38:17.310821;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1781;20:38:17.310834;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1782;20:38:17.310879;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1783;20:38:17.310885;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1784;20:38:17.310897;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1785;20:38:17.310905;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1786;20:38:17.311012;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1787;20:38:17.489753;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1788;20:38:17.489900;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
1789;20:38:17.489918;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
1790;20:38:17.490230;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
1791;20:38:17.490404;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
1792;20:38:17.490529;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
1793;20:38:17.490582;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1794;20:38:17.490590;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1795;20:38:17.490629;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1796;20:38:17.490637;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1797;20:38:17.490645;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1798;20:38:17.490817;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1799;20:38:17.490830;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1800;20:38:17.490876;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1801;20:38:17.490883;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1802;20:38:17.490894;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1803;20:38:17.490903;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1804;20:38:17.491021;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1805;20:38:17.669873;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1806;20:38:17.670147;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0097000000000000 0000000000000000 00000000
1807;20:38:17.670181;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
1808;20:38:17.670553;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
1809;20:38:17.670976;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01503100 blen=2048 desc=1372742
1810;20:38:17.671269;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372752
1811;20:38:17.671561;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
1812;20:38:17.671664;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1813;20:38:17.671679;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1814;20:38:17.671756;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173212 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1815;20:38:17.671770;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1816;20:38:17.671788;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1817;20:38:17.672588;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTL: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1818;20:38:17.672692;Dbg;deqna;4727;deqna.cpp;1191;DEQNA: Write XMTL (reg 4) = 173226 access=0
1819;20:38:17.672917;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO XMTH: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1820;20:38:17.672998;Dbg;deqna;4726;deqna.cpp;1191;DEQNA: Write XMTH (reg 5) = 000005 access=0
1821;20:38:17.673053;Dbg;deqna;4726;deqna.cpp;1216;DEQNA: TX list update pending (XMTH=000005 XMTL=173226 csr=110521)
1822;20:38:17.673093;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1823;20:38:17.673322;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff9803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 000000000000c0a8 011c000000000000 0000000000000000 00000000
1824;20:38:17.673352;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
1825;20:38:17.673559;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1826;20:38:17.673577;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1827;20:38:17.673663;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1828;20:38:17.673676;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1829;20:38:17.673700;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1830;20:38:17.673717;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1831;20:38:17.673876;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1832;20:38:17.673979;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1833;20:38:17.673995;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010521 now=010501 set=000000 clr=000020
1834;20:38:17.674020;Dbg;deqna;4727;deqna.cpp;1912;DEQNA: TX list dispatch at 1373226 (csr=010501)
1835;20:38:17.674274;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
1836;20:38:17.674554;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
1837;20:38:17.674790;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
1838;20:38:17.674887;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
1839;20:38:17.674901;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010501 now=110501 set=100000 clr=000000
1840;20:38:17.674979;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110501/100701
1841;20:38:17.674993;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110501 ie=1
1842;20:38:17.675010;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110501 vec=374 level=5
1843;20:38:17.675095;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373226 words=6
1844;20:38:17.675799;Dbg;deqna;4727;deqna.cpp;2170;DEQNA: TX EOMSG len=98 setup=0 loopback=0 (IL_clear=0 EL_set=0) csr=110501
1845;20:38:17.676023;Dbg;deqna;4727;deqna.cpp;1953;DEQNA: TX callback status=0 st1=000000 st2=001564 desc=1373236
1846;20:38:17.676475;Dbg;deqna;4727;deqna.cpp;1975;DEQNA: XI set (tx_done status=0 len=98 desc=1373226)
1847;20:38:17.676580;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110701/100701
1848;20:38:17.676595;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=110501 now=110701 set=000200 clr=000000
1849;20:38:17.676675;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110701/100701
1850;20:38:17.676692;Dbg;deqna;4727;deqna.cpp;2068;DEQNA: TX desc_read_words @ 01373242 words=6
1851;20:38:17.676893;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110701/100701
1852;20:38:17.676911;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1853;20:38:17.676997;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010501/100701
1854;20:38:17.677009;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110701 now=010501 set=000501 clr=103216
1855;20:38:17.677032;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010501 ie=1
1856;20:38:17.677048;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010501
1857;20:38:17.677510;Dbg;deqna;4727;deqna.cpp;2101;DEQNA: TX list end (V=0) - XI/XL set desc=1373242
1858;20:38:17.677605;Dbg;deqna;4727;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1859;20:38:17.677619;Dbg;deqna;4727;deqna.cpp;643;DEQNA: CSR change prev=010501 now=010721 set=000220 clr=000000
1860;20:38:17.677642;Dbg;deqna;4727;deqna.cpp;586;DEQNA: INTR assert, csr=010721 ie=1
1861;20:38:17.677658;Dbg;deqna;4727;deqna.cpp;719;DEQNA: INTR assert, csr=010721 vec=374 level=5
1862;20:38:17.677909;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010721/100701
1863;20:38:17.677927;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1864;20:38:17.678009;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1865;20:38:17.678022;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=010721 now=010521 set=000501 clr=103216
1866;20:38:17.678045;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1867;20:38:17.678060;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1868;20:38:17.678780;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1869;20:38:17.689454;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=98 status=000000 queue=0
1870;20:38:17.689727;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=98 data=5254001234562870 4e38d94008004500 0054000000007101 d6198efb22cec0a8 011e00005ea88000 0c0057690e4e0600 be9c08090a0b0c0d 0e0f101112131415 
1871;20:38:17.689766;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
1872;20:38:17.690230;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=98 to addr=01513100 blen=2048 desc=1372772
1873;20:38:17.690551;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=023046 desc=1373002
1874;20:38:17.690785;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
1875;20:38:17.690886;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1876;20:38:17.690901;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1877;20:38:17.690977;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1878;20:38:17.690991;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1879;20:38:17.691009;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1880;20:38:17.691214;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1881;20:38:17.691235;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1882;20:38:17.691321;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1883;20:38:17.691333;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1884;20:38:17.691356;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1885;20:38:17.691372;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1886;20:38:17.691478;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1887;20:38:17.809663;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1888;20:38:17.809960;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff245a 4c1db8a508060001 080006040001245a 4c1db8a5c0a80009 ffffffffffffc0a8 0101000000000000 0000000000000000 00000000
1889;20:38:17.809999;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
1890;20:38:17.810533;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01517100 blen=2048 desc=1373006
1891;20:38:17.810810;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373016
1892;20:38:17.811041;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
1893;20:38:17.811176;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1894;20:38:17.811191;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1895;20:38:17.811271;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1896;20:38:17.811284;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1897;20:38:17.811302;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1898;20:38:17.811541;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1899;20:38:17.811561;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1900;20:38:17.811645;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1901;20:38:17.811658;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1902;20:38:17.811681;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1903;20:38:17.811696;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1904;20:38:17.812446;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1905;20:38:18.209854;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=86 status=000000 queue=0
1906;20:38:18.210197;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=86 data=ffffffffffff9803 9bb4213e08004500 0048e48400004011 11c3c0a8010ec0a8 01ffe115e1150034 8abf53706f745564 7030a68cf7cceec2 7d81000100044895 
1907;20:38:18.210239;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
1908;20:38:18.210785;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=86 to addr=01523100 blen=2048 desc=1373022
1909;20:38:18.211118;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=015032 desc=1373032
1910;20:38:18.211358;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
1911;20:38:18.211495;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1912;20:38:18.211510;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1913;20:38:18.211590;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1914;20:38:18.211604;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1915;20:38:18.211623;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1916;20:38:18.211869;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1917;20:38:18.211891;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1918;20:38:18.211978;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1919;20:38:18.211992;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1920;20:38:18.212014;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1921;20:38:18.212030;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1922;20:38:18.212802;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1923;20:38:18.349840;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1924;20:38:18.350152;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c3000000000000 0000000000000000 00000000
1925;20:38:18.350190;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
1926;20:38:18.350715;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
1927;20:38:18.350998;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
1928;20:38:18.351233;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
1929;20:38:18.351373;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1930;20:38:18.351388;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1931;20:38:18.351469;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1932;20:38:18.351483;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1933;20:38:18.351502;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1934;20:38:18.351738;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1935;20:38:18.351760;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1936;20:38:18.351845;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1937;20:38:18.351858;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1938;20:38:18.351880;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1939;20:38:18.351896;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1940;20:38:18.352647;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1941;20:38:18.509860;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1942;20:38:18.510166;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
1943;20:38:18.510204;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
1944;20:38:18.510722;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01533100 blen=2048 desc=1373052
1945;20:38:18.511025;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373062
1946;20:38:18.511257;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
1947;20:38:18.511395;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1948;20:38:18.511410;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1949;20:38:18.511490;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1950;20:38:18.511505;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1951;20:38:18.511523;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1952;20:38:18.511760;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1953;20:38:18.511782;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1954;20:38:18.511867;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1955;20:38:18.511880;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1956;20:38:18.511903;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1957;20:38:18.511919;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1958;20:38:18.512684;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1959;20:38:18.589845;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1960;20:38:18.590108;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
1961;20:38:18.590145;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
1962;20:38:18.590627;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01537100 blen=2048 desc=1373066
1963;20:38:18.590992;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373076
1964;20:38:18.591226;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
1965;20:38:18.591326;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1966;20:38:18.591341;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1967;20:38:18.591417;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1968;20:38:18.591431;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1969;20:38:18.591448;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1970;20:38:18.591657;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1971;20:38:18.591678;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1972;20:38:18.591763;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1973;20:38:18.591777;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1974;20:38:18.591799;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1975;20:38:18.591815;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1976;20:38:18.591928;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1977;20:38:18.689854;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1978;20:38:18.690123;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff9803 9bb4213e08060001 0800060400019803 9bb4213ec0a8010e 000000000000c0a8 011c000000000000 0000000000000000 00000000
1979;20:38:18.690161;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
1980;20:38:18.690654;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01543100 blen=2048 desc=1373102
1981;20:38:18.691049;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373112
1982;20:38:18.691290;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
1983;20:38:18.691393;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1984;20:38:18.691408;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
1985;20:38:18.691484;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1986;20:38:18.691499;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
1987;20:38:18.691517;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
1988;20:38:18.692601;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
1989;20:38:18.692623;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
1990;20:38:18.692710;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
1991;20:38:18.692724;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
1992;20:38:18.692747;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1993;20:38:18.692763;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
1994;20:38:18.692890;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
1995;20:38:18.750561;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
1996;20:38:18.750946;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0097000000000000 0000000000000000 00000000
1997;20:38:18.750992;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
1998;20:38:18.751800;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01547100 blen=2048 desc=1373116
1999;20:38:18.752264;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373126
2000;20:38:18.752737;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
2001;20:38:18.752851;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2002;20:38:18.752868;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2003;20:38:18.752945;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2004;20:38:18.752960;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2005;20:38:18.752978;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2006;20:38:18.753306;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2007;20:38:18.753332;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2008;20:38:18.753425;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2009;20:38:18.753438;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2010;20:38:18.753463;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2011;20:38:18.753480;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2012;20:38:18.753565;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2013;20:38:19.089031;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2014;20:38:19.089229;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c5000000000000 0000000000000000 00000000
2015;20:38:19.089256;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
2016;20:38:19.089609;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01553100 blen=2048 desc=1373132
2017;20:38:19.089788;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373142
2018;20:38:19.089916;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
2019;20:38:19.089977;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2020;20:38:19.089988;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2021;20:38:19.090029;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2022;20:38:19.090037;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2023;20:38:19.090047;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2024;20:38:19.090253;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2025;20:38:19.090270;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2026;20:38:19.090320;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2027;20:38:19.090327;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2028;20:38:19.090339;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2029;20:38:19.090367;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2030;20:38:19.090411;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2031;20:38:19.229264;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=121 status=000000 queue=0
2032;20:38:19.229428;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=121 data=ffffffffffffb04a 39cb1cda08004500 006b000040004011 b67fc0a800b3c0a8 01ff8c73e5f20057 fca4312e30000000 0100020040a00d54 b415c583cd296f58 
2033;20:38:19.229451;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
2034;20:38:19.229749;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=121 to addr=01557100 blen=2048 desc=1373146
2035;20:38:19.230182;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=036475 desc=1373156
2036;20:38:19.230348;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
2037;20:38:19.230404;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2038;20:38:19.230413;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2039;20:38:19.230453;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2040;20:38:19.230461;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2041;20:38:19.230471;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2042;20:38:19.230649;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2043;20:38:19.230662;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2044;20:38:19.230707;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2045;20:38:19.230714;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2046;20:38:19.230726;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2047;20:38:19.230735;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2048;20:38:19.231306;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2049;20:38:19.429849;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2050;20:38:19.430128;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff7845 58f5956108060001 0800060400017845 58f59561c0a8000c ffffffffffffc0a8 0101000000000000 0000000000000000 00000000
2051;20:38:19.430168;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
2052;20:38:19.430742;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
2053;20:38:19.431021;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
2054;20:38:19.431257;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
2055;20:38:19.431361;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2056;20:38:19.431376;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2057;20:38:19.431455;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2058;20:38:19.431470;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2059;20:38:19.431489;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2060;20:38:19.431732;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2061;20:38:19.431754;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2062;20:38:19.431838;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2063;20:38:19.431851;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2064;20:38:19.431875;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2065;20:38:19.431892;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2066;20:38:19.431975;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2067;20:38:19.629606;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2068;20:38:19.629881;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
2069;20:38:19.629918;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
2070;20:38:19.630226;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
2071;20:38:19.630704;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01503100 blen=2048 desc=1372742
2072;20:38:19.630986;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372752
2073;20:38:19.631215;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
2074;20:38:19.631318;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2075;20:38:19.631333;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2076;20:38:19.631412;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2077;20:38:19.631426;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2078;20:38:19.631444;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2079;20:38:19.631658;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2080;20:38:19.631707;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2081;20:38:19.631797;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2082;20:38:19.631810;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2083;20:38:19.631834;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2084;20:38:19.631850;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2085;20:38:19.631931;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2086;20:38:19.789239;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2087;20:38:19.789391;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0097000000000000 0000000000000000 00000000
2088;20:38:19.789413;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
2089;20:38:19.789708;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
2090;20:38:19.789888;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
2091;20:38:19.790052;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
2092;20:38:19.790107;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2093;20:38:19.790115;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2094;20:38:19.790155;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2095;20:38:19.790163;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2096;20:38:19.790173;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2097;20:38:19.790359;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2098;20:38:19.790372;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2099;20:38:19.790417;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2100;20:38:19.790424;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2101;20:38:19.790436;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2102;20:38:19.790444;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2103;20:38:19.791005;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2104;20:38:19.869513;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2105;20:38:19.869652;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0013000000000000 0000000000000000 00000000
2106;20:38:19.869676;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
2107;20:38:19.869961;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01513100 blen=2048 desc=1372772
2108;20:38:19.870148;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373002
2109;20:38:19.870276;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
2110;20:38:19.870329;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2111;20:38:19.870337;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2112;20:38:19.870377;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2113;20:38:19.870384;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2114;20:38:19.870394;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2115;20:38:19.870567;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2116;20:38:19.870580;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2117;20:38:19.870624;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2118;20:38:19.870630;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2119;20:38:19.870642;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2120;20:38:19.870651;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2121;20:38:19.871088;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2122;20:38:19.889216;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2123;20:38:19.889351;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01e8000000000000 0000000000000000 00000000
2124;20:38:19.889368;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
2125;20:38:19.889668;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01517100 blen=2048 desc=1373006
2126;20:38:19.889844;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373016
2127;20:38:19.889970;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
2128;20:38:19.890022;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2129;20:38:19.890030;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2130;20:38:19.890069;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2131;20:38:19.890075;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2132;20:38:19.890085;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2133;20:38:19.890393;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2134;20:38:19.890407;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2135;20:38:19.890451;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2136;20:38:19.890457;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2137;20:38:19.890468;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2138;20:38:19.890477;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2139;20:38:19.890620;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2140;20:38:19.909716;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2141;20:38:19.909849;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0196000000000000 0000000000000000 00000000
2142;20:38:19.909866;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
2143;20:38:19.910161;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01523100 blen=2048 desc=1373022
2144;20:38:19.910336;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373032
2145;20:38:19.910463;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
2146;20:38:19.910515;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2147;20:38:19.910523;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2148;20:38:19.910562;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2149;20:38:19.910569;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2150;20:38:19.910578;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2151;20:38:19.910750;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2152;20:38:19.910762;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2153;20:38:19.910805;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2154;20:38:19.910812;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2155;20:38:19.910823;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2156;20:38:19.910831;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2157;20:38:19.911251;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2158;20:38:19.911638;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2159;20:38:19.911756;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01fa000000000000 0000000000000000 00000000
2160;20:38:19.911770;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
2161;20:38:19.911989;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
2162;20:38:19.912154;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
2163;20:38:19.912287;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
2164;20:38:19.912335;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2165;20:38:19.912342;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2166;20:38:19.912382;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2167;20:38:19.912389;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2168;20:38:19.912398;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2169;20:38:19.912886;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2170;20:38:19.912896;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2171;20:38:19.912938;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2172;20:38:19.912944;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2173;20:38:19.912955;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2174;20:38:19.912963;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2175;20:38:19.913458;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2176;20:38:19.913481;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2177;20:38:19.913593;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01cc000000000000 0000000000000000 00000000
2178;20:38:19.913608;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
2179;20:38:19.913839;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01533100 blen=2048 desc=1373052
2180;20:38:19.914004;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373062
2181;20:38:19.914124;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
2182;20:38:19.914171;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2183;20:38:19.914178;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2184;20:38:19.914218;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2185;20:38:19.914225;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2186;20:38:19.914233;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2187;20:38:19.915449;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2188;20:38:19.915459;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2189;20:38:19.915501;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2190;20:38:19.915507;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2191;20:38:19.915518;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2192;20:38:19.915526;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2193;20:38:19.915710;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2194;20:38:19.929233;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2195;20:38:19.929366;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0130000000000000 0000000000000000 00000000
2196;20:38:19.929382;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
2197;20:38:19.929640;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01537100 blen=2048 desc=1373066
2198;20:38:19.929819;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373076
2199;20:38:19.929944;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
2200;20:38:19.929997;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2201;20:38:19.930004;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2202;20:38:19.930044;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2203;20:38:19.930051;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2204;20:38:19.930060;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2205;20:38:19.930245;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2206;20:38:19.930257;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2207;20:38:19.930299;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2208;20:38:19.930305;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2209;20:38:19.930317;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2210;20:38:19.930325;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2211;20:38:19.930364;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2212;20:38:20.109845;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2213;20:38:20.110121;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c5000000000000 0000000000000000 00000000
2214;20:38:20.110188;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
2215;20:38:20.110715;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01543100 blen=2048 desc=1373102
2216;20:38:20.111006;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373112
2217;20:38:20.111243;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
2218;20:38:20.111381;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2219;20:38:20.111397;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2220;20:38:20.111475;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2221;20:38:20.111489;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2222;20:38:20.111508;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2223;20:38:20.111743;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2224;20:38:20.111765;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2225;20:38:20.111851;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2226;20:38:20.111864;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2227;20:38:20.111933;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2228;20:38:20.111952;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2229;20:38:20.112689;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2230;20:38:20.469864;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2231;20:38:20.470142;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
2232;20:38:20.470176;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
2233;20:38:20.470682;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01547100 blen=2048 desc=1373116
2234;20:38:20.471045;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373126
2235;20:38:20.471289;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
2236;20:38:20.471394;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2237;20:38:20.471409;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2238;20:38:20.471486;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2239;20:38:20.471500;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2240;20:38:20.471519;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2241;20:38:20.471732;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2242;20:38:20.471754;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2243;20:38:20.471838;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2244;20:38:20.471850;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2245;20:38:20.471874;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2246;20:38:20.471891;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2247;20:38:20.472002;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2248;20:38:20.669813;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2249;20:38:20.670111;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
2250;20:38:20.670146;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
2251;20:38:20.670671;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01553100 blen=2048 desc=1373132
2252;20:38:20.670946;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373142
2253;20:38:20.671180;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
2254;20:38:20.671316;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2255;20:38:20.671333;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2256;20:38:20.671412;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2257;20:38:20.671426;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2258;20:38:20.671445;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2259;20:38:20.671686;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2260;20:38:20.671706;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2261;20:38:20.671790;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2262;20:38:20.671803;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2263;20:38:20.671825;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2264;20:38:20.671841;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2265;20:38:20.672588;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2266;20:38:20.870185;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=219 status=000000 queue=0
2267;20:38:20.870468;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=219 data=ffffffffffff0010 752b42e908004500 00cd000040004011 781ec0a8015affff ffffe2a004d200b9 63f348656c6c6f20 74686572652e2049 20616d2061742031 
2268;20:38:20.870508;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
2269;20:38:20.871047;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=219 to addr=01557100 blen=2048 desc=1373146
2270;20:38:20.871866;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=117637 desc=1373156
2271;20:38:20.872099;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
2272;20:38:20.872230;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2273;20:38:20.872247;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2274;20:38:20.872328;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2275;20:38:20.872344;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2276;20:38:20.872362;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2277;20:38:20.872598;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2278;20:38:20.872620;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2279;20:38:20.872708;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2280;20:38:20.872722;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2281;20:38:20.872743;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2282;20:38:20.872760;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2283;20:38:20.873509;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2284;20:38:20.873567;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=243 status=000000 queue=0
2285;20:38:20.873826;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=243 data=ffffffffffff0010 752b42e908004500 00e5000040004011 7806c0a8015affff ffffe2a1d01a00d1 b8b948656c6c6f20 74686572652e2049 20616d2061742031 
2286;20:38:20.873860;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
2287;20:38:20.874374;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=243 to addr=01563100 blen=2048 desc=1373162
2288;20:38:20.875256;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=133667 desc=1373172
2289;20:38:20.875488;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
2290;20:38:20.875587;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2291;20:38:20.875601;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2292;20:38:20.875679;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2293;20:38:20.875693;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2294;20:38:20.875711;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2295;20:38:20.875915;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2296;20:38:20.875934;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2297;20:38:20.876015;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2298;20:38:20.876027;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2299;20:38:20.876050;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2300;20:38:20.876066;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2301;20:38:20.876175;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2302;20:38:20.876847;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2303;20:38:20.877086;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0013000000000000 0000000000000000 00000000
2304;20:38:20.877115;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
2305;20:38:20.877413;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
2306;20:38:20.877823;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01503100 blen=2048 desc=1372742
2307;20:38:20.878091;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372752
2308;20:38:20.878319;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
2309;20:38:20.878446;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2310;20:38:20.878460;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2311;20:38:20.878538;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2312;20:38:20.878552;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2313;20:38:20.878569;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2314;20:38:20.878892;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2315;20:38:20.878913;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2316;20:38:20.878995;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2317;20:38:20.879008;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2318;20:38:20.879030;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2319;20:38:20.879046;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2320;20:38:20.879797;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2321;20:38:20.889988;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2322;20:38:20.890234;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01e8000000000000 0000000000000000 00000000
2323;20:38:20.890272;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
2324;20:38:20.890980;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
2325;20:38:20.891275;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
2326;20:38:20.891510;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
2327;20:38:20.891611;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2328;20:38:20.891626;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2329;20:38:20.891704;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2330;20:38:20.891719;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2331;20:38:20.891737;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2332;20:38:20.891945;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2333;20:38:20.891964;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2334;20:38:20.892049;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2335;20:38:20.892063;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2336;20:38:20.892085;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2337;20:38:20.892101;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2338;20:38:20.892210;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2339;20:38:20.909739;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2340;20:38:20.909887;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0196000000000000 0000000000000000 00000000
2341;20:38:20.909924;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
2342;20:38:20.910235;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01513100 blen=2048 desc=1372772
2343;20:38:20.910418;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373002
2344;20:38:20.910546;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
2345;20:38:20.910601;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2346;20:38:20.910609;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2347;20:38:20.910648;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2348;20:38:20.910656;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2349;20:38:20.910665;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2350;20:38:20.910841;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2351;20:38:20.910855;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2352;20:38:20.910900;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2353;20:38:20.910906;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2354;20:38:20.910918;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2355;20:38:20.910927;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2356;20:38:20.911026;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2357;20:38:20.911731;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2358;20:38:20.911849;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01fa000000000000 0000000000000000 00000000
2359;20:38:20.911865;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
2360;20:38:20.912121;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01517100 blen=2048 desc=1373006
2361;20:38:20.912288;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373016
2362;20:38:20.912409;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
2363;20:38:20.912458;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2364;20:38:20.912465;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2365;20:38:20.912505;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2366;20:38:20.912513;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2367;20:38:20.912521;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2368;20:38:20.912898;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2369;20:38:20.912909;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2370;20:38:20.912951;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2371;20:38:20.912958;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2372;20:38:20.912969;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2373;20:38:20.912977;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2374;20:38:20.913127;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2375;20:38:20.913577;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2376;20:38:20.913693;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01cc000000000000 0000000000000000 00000000
2377;20:38:20.913708;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
2378;20:38:20.913925;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01523100 blen=2048 desc=1373022
2379;20:38:20.914087;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373032
2380;20:38:20.914237;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
2381;20:38:20.914285;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2382;20:38:20.914292;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2383;20:38:20.914332;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2384;20:38:20.914339;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2385;20:38:20.914348;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2386;20:38:20.915428;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2387;20:38:20.915439;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2388;20:38:20.915480;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2389;20:38:20.915486;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2390;20:38:20.915497;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2391;20:38:20.915506;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2392;20:38:20.915546;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2393;20:38:20.929205;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2394;20:38:20.929338;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 0130000000000000 0000000000000000 00000000
2395;20:38:20.929356;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
2396;20:38:20.929625;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
2397;20:38:20.929804;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
2398;20:38:20.929925;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
2399;20:38:20.929977;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2400;20:38:20.929984;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2401;20:38:20.930023;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2402;20:38:20.930030;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2403;20:38:20.930039;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2404;20:38:20.930206;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2405;20:38:20.930219;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2406;20:38:20.930262;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2407;20:38:20.930269;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2408;20:38:20.930281;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2409;20:38:20.930288;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2410;20:38:20.930716;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2411;20:38:20.989236;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=86 status=000000 queue=0
2412;20:38:20.989383;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=86 data=fffffffffffff430 b9c3afae08004500 0048816200008011 342ac0a801c9c0a8 01ffe115e1150034 3bae53706f745564 7030571624fc730f fe03000100044895 
2413;20:38:20.989401;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
2414;20:38:20.989693;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=86 to addr=01533100 blen=2048 desc=1373052
2415;20:38:20.989912;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=015032 desc=1373062
2416;20:38:20.990043;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
2417;20:38:20.990096;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2418;20:38:20.990103;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2419;20:38:20.990142;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2420;20:38:20.990149;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2421;20:38:20.990158;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2422;20:38:20.990332;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2423;20:38:20.990346;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2424;20:38:20.990392;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2425;20:38:20.990399;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2426;20:38:20.990411;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2427;20:38:20.990419;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2428;20:38:20.990503;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2429;20:38:21.029246;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2430;20:38:21.029387;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff0010 7f78e6ec08060001 0800060400010010 7f78e6ecc0a801c4 000000000000c0a8 0015000000000000 0000000000000000 00000000
2431;20:38:21.029404;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
2432;20:38:21.029710;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01537100 blen=2048 desc=1373066
2433;20:38:21.029896;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373076
2434;20:38:21.030023;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
2435;20:38:21.030075;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2436;20:38:21.030083;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2437;20:38:21.030122;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2438;20:38:21.030129;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2439;20:38:21.030138;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2440;20:38:21.030320;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2441;20:38:21.030333;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2442;20:38:21.030378;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2443;20:38:21.030385;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2444;20:38:21.030396;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2445;20:38:21.030404;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2446;20:38:21.030663;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2447;20:38:21.149221;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2448;20:38:21.149372;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c5000000000000 0000000000000000 00000000
2449;20:38:21.149389;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
2450;20:38:21.149694;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01543100 blen=2048 desc=1373102
2451;20:38:21.149879;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373112
2452;20:38:21.150006;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
2453;20:38:21.150062;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2454;20:38:21.150070;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2455;20:38:21.150110;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2456;20:38:21.150118;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2457;20:38:21.150128;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2458;20:38:21.150309;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2459;20:38:21.150322;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2460;20:38:21.150366;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2461;20:38:21.150373;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2462;20:38:21.150385;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2463;20:38:21.150393;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2464;20:38:21.150788;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2465;20:38:21.529863;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2466;20:38:21.530147;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
2467;20:38:21.530179;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
2468;20:38:21.530718;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01547100 blen=2048 desc=1373116
2469;20:38:21.531005;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373126
2470;20:38:21.531299;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
2471;20:38:21.531433;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2472;20:38:21.531449;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2473;20:38:21.531528;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2474;20:38:21.531543;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2475;20:38:21.531562;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2476;20:38:21.531807;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2477;20:38:21.531829;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2478;20:38:21.531915;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2479;20:38:21.531928;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2480;20:38:21.531951;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2481;20:38:21.531967;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2482;20:38:21.532713;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2483;20:38:21.770650;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2484;20:38:21.770940;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff74ac b933a1e908060001 08000604000174ac b933a1e9c0a80004 ffffffffffffc0a8 0101020014000200 0f00000000000000 00000000
2485;20:38:21.770977;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
2486;20:38:21.771766;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01553100 blen=2048 desc=1373132
2487;20:38:21.772126;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373142
2488;20:38:21.772428;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
2489;20:38:21.772538;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2490;20:38:21.772556;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2491;20:38:21.772634;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2492;20:38:21.772650;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2493;20:38:21.772668;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2494;20:38:21.773330;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2495;20:38:21.773357;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2496;20:38:21.773451;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2497;20:38:21.773464;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2498;20:38:21.773487;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2499;20:38:21.773504;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2500;20:38:21.774114;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2501;20:38:22.269863;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2502;20:38:22.270165;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c5000000000000 0000000000000000 00000000
2503;20:38:22.270200;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
2504;20:38:22.270802;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01557100 blen=2048 desc=1373146
2505;20:38:22.271088;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373156
2506;20:38:22.271324;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
2507;20:38:22.271432;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2508;20:38:22.271448;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2509;20:38:22.271527;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2510;20:38:22.271540;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2511;20:38:22.271558;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2512;20:38:22.271800;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2513;20:38:22.271824;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2514;20:38:22.271914;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2515;20:38:22.271927;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2516;20:38:22.271950;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2517;20:38:22.271967;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2518;20:38:22.272051;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2519;20:38:22.549858;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2520;20:38:22.550174;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
2521;20:38:22.550210;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
2522;20:38:22.550746;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
2523;20:38:22.551050;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
2524;20:38:22.551285;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
2525;20:38:22.551426;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2526;20:38:22.551442;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2527;20:38:22.551524;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2528;20:38:22.551538;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2529;20:38:22.551557;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2530;20:38:22.551798;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2531;20:38:22.551820;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2532;20:38:22.551906;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2533;20:38:22.551918;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2534;20:38:22.551941;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2535;20:38:22.551957;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2536;20:38:22.552708;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2537;20:38:22.589573;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2538;20:38:22.589828;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
2539;20:38:22.589866;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373176 words=4
2540;20:38:22.590186;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372742 words=4
2541;20:38:22.590618;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01503100 blen=2048 desc=1372742
2542;20:38:22.590887;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372752
2543;20:38:22.591178;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372756)
2544;20:38:22.591279;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2545;20:38:22.591294;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2546;20:38:22.591371;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2547;20:38:22.591384;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2548;20:38:22.591402;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2549;20:38:22.591612;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2550;20:38:22.591632;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2551;20:38:22.591715;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2552;20:38:22.591727;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2553;20:38:22.591750;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2554;20:38:22.591767;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2555;20:38:22.592108;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2556;20:38:22.789863;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2557;20:38:22.790132;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffffc82b 96b611ec00060001 af81010000000000 0000000000000000 0000000000000000 0000000000000000 0000000000000000 00000000
2558;20:38:22.790169;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372756 words=4
2559;20:38:22.790721;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01507100 blen=2048 desc=1372756
2560;20:38:22.790998;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1372766
2561;20:38:22.791234;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1372772)
2562;20:38:22.791336;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2563;20:38:22.791351;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2564;20:38:22.791428;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2565;20:38:22.791441;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2566;20:38:22.791459;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2567;20:38:22.791716;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2568;20:38:22.791738;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2569;20:38:22.791822;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2570;20:38:22.791834;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2571;20:38:22.791857;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2572;20:38:22.791874;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2573;20:38:22.792635;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2574;20:38:23.309867;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2575;20:38:23.310152;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c5000000000000 0000000000000000 00000000
2576;20:38:23.310228;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01372772 words=4
2577;20:38:23.310794;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01513100 blen=2048 desc=1372772
2578;20:38:23.311078;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373002
2579;20:38:23.311317;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373006)
2580;20:38:23.311455;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2581;20:38:23.311471;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2582;20:38:23.311551;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2583;20:38:23.311566;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2584;20:38:23.311583;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2585;20:38:23.311825;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2586;20:38:23.311848;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2587;20:38:23.311933;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2588;20:38:23.311946;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2589;20:38:23.311969;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2590;20:38:23.311985;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2591;20:38:23.312744;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2592;20:38:23.549859;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2593;20:38:23.550172;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008004500 0020ac6d40004011 ccb6c0a80101ffff ffffc8782711000c 4da3010000000000 0000000000000000 00000000
2594;20:38:23.550211;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373006 words=4
2595;20:38:23.550735;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01517100 blen=2048 desc=1373006
2596;20:38:23.551033;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373016
2597;20:38:23.551266;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373022)
2598;20:38:23.551399;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2599;20:38:23.551415;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2600;20:38:23.551494;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2601;20:38:23.551507;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2602;20:38:23.551526;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2603;20:38:23.551765;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2604;20:38:23.551787;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2605;20:38:23.551875;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2606;20:38:23.551888;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2607;20:38:23.551911;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2608;20:38:23.551926;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2609;20:38:23.552669;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2610;20:38:23.609877;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2611;20:38:23.610180;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
2612;20:38:23.610218;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373022 words=4
2613;20:38:23.610723;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01523100 blen=2048 desc=1373022
2614;20:38:23.611026;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373032
2615;20:38:23.611260;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373036)
2616;20:38:23.611396;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2617;20:38:23.611411;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2618;20:38:23.611489;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2619;20:38:23.611503;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2620;20:38:23.611522;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2621;20:38:23.611755;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2622;20:38:23.611776;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2623;20:38:23.611861;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2624;20:38:23.611874;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2625;20:38:23.611896;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2626;20:38:23.611912;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2627;20:38:23.612700;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2628;20:38:23.889577;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2629;20:38:23.889892;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff245a 4c1db8a508060001 080006040001245a 4c1db8a5c0a80009 ffffffffffffc0a8 0101000000000000 0000000000000000 00000000
2630;20:38:23.889937;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373036 words=4
2631;20:38:23.890553;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01527100 blen=2048 desc=1373036
2632;20:38:23.890841;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373046
2633;20:38:23.891076;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373052)
2634;20:38:23.891220;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2635;20:38:23.891237;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2636;20:38:23.891319;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2637;20:38:23.891334;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2638;20:38:23.891353;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2639;20:38:23.891606;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2640;20:38:23.891630;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2641;20:38:23.891720;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2642;20:38:23.891733;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2643;20:38:23.891757;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2644;20:38:23.891774;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2645;20:38:23.892517;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2646;20:38:24.229928;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=121 status=000000 queue=0
2647;20:38:24.230226;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=121 data=ffffffffffffb04a 39cb1cda08004500 006b000040004011 b67fc0a800b3c0a8 01ffd684e5f20057 b293312e30000000 0100020040a00d54 b415c583cd296f58 
2648;20:38:24.230270;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373052 words=4
2649;20:38:24.230868;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=121 to addr=01533100 blen=2048 desc=1373052
2650;20:38:24.231717;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=036475 desc=1373062
2651;20:38:24.231958;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373066)
2652;20:38:24.232068;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2653;20:38:24.232084;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2654;20:38:24.232163;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2655;20:38:24.232179;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2656;20:38:24.232197;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2657;20:38:24.232414;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2658;20:38:24.232436;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2659;20:38:24.232523;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2660;20:38:24.232536;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2661;20:38:24.232560;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2662;20:38:24.232610;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2663;20:38:24.232696;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2664;20:38:24.349454;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2665;20:38:24.349733;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01c5000000000000 0000000000000000 00000000
2666;20:38:24.349772;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373066 words=4
2667;20:38:24.350301;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01537100 blen=2048 desc=1373066
2668;20:38:24.350577;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373076
2669;20:38:24.350811;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373102)
2670;20:38:24.350948;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2671;20:38:24.350964;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2672;20:38:24.351045;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2673;20:38:24.351059;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2674;20:38:24.351079;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2675;20:38:24.351319;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2676;20:38:24.351342;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2677;20:38:24.351428;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2678;20:38:24.351441;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2679;20:38:24.351463;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2680;20:38:24.351479;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2681;20:38:24.352222;Dbg;deqna;4726;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2682;20:38:24.469963;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2683;20:38:24.470230;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff6462 6622847608060001 0800060400016462 66228476c0a80109 000000000000c0a8 010d000000000000 0000000000000000 00000000
2684;20:38:24.470267;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373102 words=4
2685;20:38:24.470762;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01543100 blen=2048 desc=1373102
2686;20:38:24.471102;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373112
2687;20:38:24.471339;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373116)
2688;20:38:24.471440;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2689;20:38:24.471455;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2690;20:38:24.471532;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2691;20:38:24.471545;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2692;20:38:24.471563;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2693;20:38:24.471774;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2694;20:38:24.471795;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2695;20:38:24.471881;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2696;20:38:24.471894;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2697;20:38:24.471916;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2698;20:38:24.471933;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2699;20:38:24.472046;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2700;20:38:24.569234;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2701;20:38:24.569384;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffffd0d2 b08e8ca608060001 080006040001d0d2 b08e8ca6c0a8008b 000000000000c0a8 008b000000000000 0000000000000000 00000000
2702;20:38:24.569407;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373116 words=4
2703;20:38:24.569729;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01547100 blen=2048 desc=1373116
2704;20:38:24.569941;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373126
2705;20:38:24.570071;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373132)
2706;20:38:24.570126;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2707;20:38:24.570134;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2708;20:38:24.570173;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2709;20:38:24.570180;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2710;20:38:24.570190;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2711;20:38:24.570369;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2712;20:38:24.570383;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2713;20:38:24.570428;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2714;20:38:24.570435;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2715;20:38:24.570447;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2716;20:38:24.570455;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2717;20:38:24.570881;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2718;20:38:24.629211;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2719;20:38:24.629371;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff506b 4b43b2a608060001 080006040001506b 4b43b2a6c0a80111 000000000000c0a8 010d000000000000 0000000000000000 00000000
2720;20:38:24.629407;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373132 words=4
2721;20:38:24.629698;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01553100 blen=2048 desc=1373132
2722;20:38:24.629874;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373142
2723;20:38:24.629999;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373146)
2724;20:38:24.630054;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2725;20:38:24.630062;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2726;20:38:24.630102;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2727;20:38:24.630109;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2728;20:38:24.630118;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2729;20:38:24.630289;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2730;20:38:24.630301;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2731;20:38:24.630346;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2732;20:38:24.630353;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2733;20:38:24.630364;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2734;20:38:24.630372;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2735;20:38:24.630514;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2736;20:38:25.009888;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2737;20:38:25.010182;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01df000000000000 0000000000000000 00000000
2738;20:38:25.010225;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373146 words=4
2739;20:38:25.010771;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01557100 blen=2048 desc=1373146
2740;20:38:25.011102;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373156
2741;20:38:25.011335;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373162)
2742;20:38:25.011444;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2743;20:38:25.011460;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2744;20:38:25.011539;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2745;20:38:25.011554;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2746;20:38:25.011573;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2747;20:38:25.011789;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2748;20:38:25.011812;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2749;20:38:25.011897;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2750;20:38:25.011910;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2751;20:38:25.011933;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2752;20:38:25.011984;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2753;20:38:25.012071;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2754;20:38:25.012729;Dbg;deqna;4726;deqna.cpp;1351;DEQNA: Enqueue RX type=2 len=60 status=000000 queue=0
2755;20:38:25.012967;Dbg;deqna;4726;deqna.cpp;1378;DEQNA: ENQ DBG type=2 len=60 data=ffffffffffff2870 4e38d94008060001 0800060400012870 4e38d940c0a80101 000000000000c0a8 01ea000000000000 0000000000000000 00000000
2756;20:38:25.013008;Dbg;deqna;4726;deqna.cpp;1597;DEQNA: RX desc_read_words @ 01373162 words=4
2757;20:38:25.013867;Dbg;deqna;4726;deqna.cpp;1705;DEQNA: RX deliver type=2 rbl=60 to addr=01563100 blen=2048 desc=1373162
2758;20:38:25.014206;Dbg;deqna;4726;deqna.cpp;1782;DEQNA: RX status type=2 st1=000370 st2=000000 desc=1373172
2759;20:38:25.014506;Dbg;deqna;4726;deqna.cpp;1849;DEQNA: RI set (rx_processed=1 queue=0 rbdl=1373176)
2760;20:38:25.014608;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2761;20:38:25.014623;Dbg;deqna;4726;deqna.cpp;643;DEQNA: CSR change prev=010521 now=110521 set=100000 clr=000000
2762;20:38:25.014701;Dbg;deqna;4726;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2763;20:38:25.014716;Dbg;deqna;4726;deqna.cpp;586;DEQNA: INTR assert, csr=110521 ie=1
2764;20:38:25.014735;Dbg;deqna;4726;deqna.cpp;719;DEQNA: INTR assert, csr=110521 vec=374 level=5
2765;20:38:25.014942;Dbg;deqna;4720;qunibusdevice.cpp;249;DATO CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=110521/100701
2766;20:38:25.014963;Dbg;deqna;4720;deqna.cpp;1191;DEQNA: Write CSR (reg 7) = 100701 access=0
2767;20:38:25.015045;Dbg;deqna;4720;qunibusdevice.cpp;249;update_csr_reg CSR: STA0=177522 STA1=177524 RCLL=177400/172742 RCLH=177422/000005 XMTL=177464/173226 XMTH=177526/000005 VECTOR=000774/000774 CSR=010521/100701
2768;20:38:25.015058;Dbg;deqna;4720;deqna.cpp;643;DEQNA: CSR change prev=110521 now=010521 set=000501 clr=103216
2769;20:38:25.015082;Dbg;deqna;4720;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
2770;20:38:25.015099;Dbg;deqna;4720;deqna.cpp;725;DEQNA: INTR deassert, csr=010521
2771;20:38:25.015441;Dbg;deqna;4727;deqna.cpp;595;DEQNA: INTR deassert, csr=010521 ie=1
root@qbone:~#