1                                	.title	M9312 'DL' BOOT prom for RL11 controller
       2                                
       3                                	; This source code is a modified copy of the DEC M9312 23-751A9 boot PROM.
       4                                	;
       5                                	; This boot PROM is for the RL11 controller with RL01/RL02 drives.
       6                                	;
       7                                	; Multiple units and/or CSR addresses are supported via different entry points.
       8                                	;
       9                                
      10 174400                         rlcsr	=174400 			; std RL11 csrbase
      11                                
      12 000000                         rlcs	=+0				; control/status
      13 000002                         rlba	=+2				; bus address
      14 000004                         rlda	=+4				; disk address
      15 000006                         rlmp	=+6				; multipurpose
      16                                
      17 000004                         cmstat	=2*2				; get status
      18 000006                         cmseek	=3*2				; seek
      19 000010                         cmrdhd	=4*2				; read header
      20 000014                         cmrdda	=6*2				; read data
      21                                
      22                                	.asect
      23                                	; ---- Simple boot drive 0 from 0
      24 000000                         	. = 0
      25 000000 000137  010000          	jmp	@#start0
      26                                
      27                                	; ---- Reboot drive 0 on power event
      28 000024                         	. = 24				; Power ON/OFF
      29 000024 010000                  	.word	     start0		; PC
      30 000026 000340                  	.word	     340		; PSW priority level 7
      31                                
      32                                	; ---- catch EVENT/LTC interrupt on QBUS
      33 000100                         	. = 100 			; EVENT
      34 000100 010204                  	.word	     catchi		; PC
      35 000102 000340                  	.word	     340		; PSW priority level 7
      36                                
      37                                
      38                                	; ----- Main boot addresses
      39 010000                         	.=10000 			;  arbitrary position > 3000
      40 007776                         stack = . - 2
      41                                
      42                                start:
      43                                	; 4 unit numbers => 4 entry addresses
      44                                start0:
      45 010000 012700  000000          	mov	#0,r0
      46 010004 000413                  	br	dlnr
      47 010006 000240                  	nop
      48                                start1:
      49 010010 012700  000001          	mov	#1,r0
      50 010014 000407                  	br	dlnr
      51 010016 000240                  	nop
      52                                start2:
      53 010020 012700  000002          	mov	#2,r0
      54 010024 000403                  	br	dlnr
      55 010026 000240                  	nop
      56                                start3:
      57 010030 012700  000003          	mov	#3,r0
      58                                
      59                                dlnr:
      60 010034 012706  007776          	mov	#stack,sp		; setup stack
      61 010040 012701  174400          	mov	#rlcsr,r1		; boot std csr, unit <R0>
      62                                
      63                                	; --------------------------------------------------
      64                                
      65 010044 010003                  	mov	r0,r3			; save unit number
      66 010046 000303                  	swab	r3			; unit number in upper byte
      67 010050 010311                  	mov	r3,(r1) 		; set unit, NOP cmd
      68                                
      69 010052 012761  000013  000004  	mov	#013,rlda(r1)		; subcmd reset+getstatus
      70 010060 052703  000004          	bis	#cmstat,r3		; get status cmd (r3lo is 0)
      71 010064 010311                  	mov	r3,(r1) 		; execute
      72 010066 105711                  1$:	tstb	(r1)			; test for ready
      73 010070 100376                  	bpl	1$			; wait
      74                                
      75 010072 105003                  	clrb	r3			; unit number in upper byte
      76 010074 052703  000010          	bis	#cmrdhd,r3		; read header cmd
      77 010100 010311                  	mov	r3,(r1) 		; execute
      78 010102 105711                  2$:	tstb	(r1)			; test for ready
      79 010104 100376                  	bpl	2$			; wait
      80                                
      81 010106 016102  000006          	mov	rlmp(r1),r2		; retrieve cyl/head/sector
      82 010112 042702  000077          	bic	#77,r2			; set sector to zero
      83 010116 005202                  	inc	r2			; set head 0, seek to cyl 0
      84 010120 010261  000004          	mov	r2,rlda(r1)		; into da for seek
      85 010124 105003                  	clrb	r3			; unit number in upper byte
      86 010126 052703  000006          	bis	#cmseek,r3		; seek cmd
      87 010132 010311                  	mov	r3,(r1) 		; execute
      88 010134 105711                  3$:	tstb	(r1)			; test for ready
      89 010136 100376                  	bpl	3$			; wait
      90                                
      91 010140 005061  000004          	clr	rlda(r1)		; select cyl0/head0/sector0
      92 010144 012761  177000  000006  	mov	#-512.,rlmp(r1) 	; set word count
      93 010152 105003                  	clrb	r3			; unit number in upper byte
      94 010154 052703  000014          	bis	#cmrdda,r3		; read data cmd
      95 010160 010311                  	mov	r3,(r1) 		; execute
      96 010162 105711                  4$:	tstb	(r1)			; test for ready
      97 010164 100376                  	bpl	4$			; wait
      98                                
      99 010166 005711                  	tst	(r1)			; test for error
     100 010170 100002                  	bpl	5$			; br if ok
     101 010172 000005                  	reset				; ERROR - reset the world
     102 010174 000717                  	br     dlnr			; retry. r0 unchanged
     103                                
     104 010176 042711  000377          5$:	bic	#377,(r1)		; execute nop cmd
     105 010202 005007                  	clr	pc			; jump to bootstrap at zero
     106                                
     107                                
     108                                	; dummy ISR to catch interrupts
     109                                catchi:
     110 010204 000002                  	rti
     111                                
     112                                	.end
     112