--- ./src/include/storage/s_lock.h_orig	2025-10-23 00:27:51.646359148 -0500
+++ ./src/include/storage/s_lock.h	2025-10-23 00:35:30.276087698 -0500
@@ -398,56 +398,18 @@
 
 #define TAS(lock) tas(lock)
 
-/* On PPC, it's a win to use a non-locking test before the lwarx */
+/* On PPC, use the compiler provided Built-in functions for atomic memory
+ * exchange operations.
+ */
 #define TAS_SPIN(lock)	(*(lock) ? 1 : TAS(lock))
 
-/*
- * The second operand of addi can hold a constant zero or a register number,
- * hence constraint "=&b" to avoid allocating r0.  "b" stands for "address
- * base register"; most operands having this register-or-zero property are
- * address bases, e.g. the second operand of lwax.
- *
- * NOTE: per the Enhanced PowerPC Architecture manual, v1.0 dated 7-May-2002,
- * an isync is a sufficient synchronization barrier after a lwarx/stwcx loop.
- * But if the spinlock is in ordinary memory, we can use lwsync instead for
- * better performance.
- */
 static __inline__ int
 tas(volatile slock_t *lock)
 {
-	slock_t _t;
-	int _res;
-
-	__asm__ __volatile__(
-"	lwarx   %0,0,%3,1	\n"
-"	cmpwi   %0,0		\n"
-"	bne     1f			\n"
-"	addi    %0,%0,1		\n"
-"	stwcx.  %0,0,%3		\n"
-"	beq     2f			\n"
-"1: \n"
-"	li      %1,1		\n"
-"	b       3f			\n"
-"2: \n"
-"	lwsync				\n"
-"	li      %1,0		\n"
-"3: \n"
-:	"=&b"(_t), "=r"(_res), "+m"(*lock)
-:	"r"(lock)
-:	"memory", "cc");
-	return _res;
+	return __sync_lock_test_and_set(lock, 1);
 }
 
-/*
- * PowerPC S_UNLOCK is almost standard but requires a "sync" instruction.
- * But we can use lwsync instead for better performance.
- */
-#define S_UNLOCK(lock)	\
-do \
-{ \
-	__asm__ __volatile__ ("	lwsync \n" ::: "memory"); \
-	*((volatile slock_t *) (lock)) = 0; \
-} while (0)
+#define S_UNLOCK(lock) __sync_lock_release(lock)
 
 #endif /* powerpc */